SDCR

Provides EL3 configuration options for self-hosted debug, trace, and the Performance Monitors Extension.

Configuration

This register is present only when EL3 is capable of using AArch32. Otherwise, direct accesses to SDCR are UNDEFINED.

Attributes

Field descriptions

Bits [31:29]

MTPME, bit [28]
When FEAT_MTPMU is implemented:

Multi-threaded PMU Enable. Enables use of the PMEVTYPER<n>.MT bits.

MTPME	Meaning
0b0	FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>.MT is 0.
0b1	PMEVTYPER<n>.MT bits not affected by this bit.

If FEAT_MTPMU is disabled for any other PE in the system that has the same level 1 Affinity as the PE, it is IMPLEMENTATION DEFINED whether the PE behaves as if this bit is 0.

The reset behavior of this field is:

On a Cold reset, in a system where the PE resets into EL3, this field resets to 1.

Otherwise:

TDCC, bit [27]
When FEAT_FGT is implemented:

Trap DCC. Traps use of the Debug Comms Channel in modes other than Monitor mode to Monitor mode.

TDCC	Meaning
0b0	This control does not cause any register accesses to be trapped.
0b1	Accesses to the DCC registers in modes other than Monitor mode generate a Monitor Trap exception, unless the access also generates a higher priority exception. Traps on the DCC data transfer registers are ignored when the PE is in Debug state.

TDCC

Meaning

0b0

This control does not cause any register accesses to be trapped.

0b1

Accesses to the DCC registers in modes other than Monitor mode generate a Monitor Trap exception, unless the access also generates a higher priority exception.

Traps on the DCC data transfer registers are ignored when the PE is in Debug state.

The DCC registers trapped by this control are:

DBGDTRRXext, DBGDTRTXext, DBGDSCRint, DBGDCCINT, and, when the PE is in Non-debug state, DBGDTRRXint and DBGDTRTXint.

When the PE is in Debug state, SDCR.TDCC does not trap any accesses to:

DBGDTRRXint and DBGDTRTXint.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [26:24]

SCCD, bit [23]
When FEAT_PMUv3p5 is implemented:

Secure Cycle Counter Disable. Prohibits PMCCNTR from counting in Secure state and EL3.

SCCD	Meaning
0b0	Cycle counting by PMCCNTR is not affected by this mechanism.
0b1	Cycle counting by PMCCNTR is prohibited in Secure state and EL3.

This field does not affect the CPU_CYCLES event or any other event that counts cycles.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.

Otherwise:

Bit [22]

EPMAD, bit [21]
When FEAT_Debugv8p4 is implemented and FEAT_PMUv3 is implemented:

External Performance Monitors Non-secure access disable. Controls Non-secure access to Performance Monitors registers by an external debugger.

EPMAD	Meaning
0b0	Non-secure access to the Performance Monitors registers from an external debugger is permitted.
0b1	Non-secure access to the Performance Monitors registers from an external debugger is not permitted.

If the Performance Monitors Extension does not support external debug interface accesses, this bit is RES0.

Otherwise, if EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.

When FEAT_PMUv3 is implemented:

External Performance Monitors access disable. Controls access to Performance Monitors registers by an external debugger.

EPMAD	Meaning
0b0	Access to Performance Monitors registers from an external debugger is permitted.
0b1	Access to Performance Monitors registers from an external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface.

If the Performance Monitors Extension does not support external debug interface accesses, this bit is RES0.

Otherwise, if EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.

Otherwise:

EDAD, bit [20]
When FEAT_Debugv8p4 is implemented:

External debug Non-secure access disable. Controls Non-secure access to breakpoint, watchpoint, and OSLAR_EL1 registers by an external debugger.

EDAD	Meaning
0b0	Non-secure access to debug registers from an external debugger is permitted.
0b1	Non-secure access to breakpoint registers, watchpoint registers, and OSLAR_EL1 from an external debugger is not permitted.

If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.

When FEAT_Debugv8p2 is implemented:

External debug access disable. Controls access to breakpoint, watchpoint, and OSLAR_EL1 registers by an external debugger.

EDAD	Meaning
0b0	Access to debug registers from an external debugger is permitted.
0b1	Access to breakpoint registers, watchpoint registers, and OSLAR_EL1 from an external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface.

If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.

Otherwise:

External debug access disable. Controls access to breakpoint, watchpoint, and optionally OSLAR_EL1 registers by an external debugger.

EDAD

Meaning

0b0

Access to debug registers from an external debugger is permitted.

0b1

Access to breakpoint registers and watchpoint registers from an external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface.

It is IMPLEMENTATION DEFINED whether access to the OSLAR_EL1 register from an external debugger is permitted or not permitted.

If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.

TTRF, bit [19]
When FEAT_TRF is implemented:

Trap Trace Filter controls. Controls whether accesses in modes other than Monitor mode to the trace filter control registers generate a Monitor Trap exception.

TTRF	Meaning
0b0	Accesses to HTRFCR and TRFCR are not affected by this control bit.
0b1	When not in Monitor mode, accesses to HTRFCR and TRFCR generate a Monitor Trap exception, unless the access generates a higher priority exception.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.

Otherwise:

STE, bit [18]
When FEAT_TRF is implemented:

Secure Trace Enable. This bit enables tracing in Secure state and controls the level of authentication required by an external debugger to enable external tracing.

STE	Meaning
0b0	Trace is prohibited in Secure state unless overridden by the IMPLEMENTATION DEFINED authentication interface.
0b1	Trace in Secure state is not affected by this bit.

This bit also controls the level of authentication required by an external debugger to enable external tracing. See 'Register controls to enable self-hosted trace'.

If EL3 is not implemented and the Effective value of SCR.NS is 0, the PE behaves as if this bit is set to 1.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.

Otherwise:

SPME, bit [17]
When FEAT_PMUv3 is implemented and FEAT_Debugv8p2 is implemented:

Secure Performance Monitors Enable. Controls event counting in Secure state.

SPME	Meaning
0b0	Event counting is prohibited in Secure state. If PMCR.DP is 1, PMCCNTR is disabled in Secure state. Otherwise, PMCCNTR is not affected by this mechanism.
0b1	Event counting and PMCCNTR are not affected by this mechanism.

This field affects the operation of all event counters in Secure state, and if PMCR.DP is 1, the operation of PMCCNTR in Secure state. When PMCR.DP is 0, PMCCNTR is not affected by this field.

If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.

When FEAT_PMUv3 is implemented:

Secure Performance Monitors Enable. Controls event counting in Secure state.

SPME	Meaning
0b0	If ExternalSecureNoninvasiveDebugEnabled() is FALSE, event counting is prohibited in Secure state, and if PMCR.DP is 1, PMCCNTR is disabled in Secure state.
0b1	Event counting and PMCCNTR are not affected by this mechanism.

If ExternalSecureNoninvasiveDebugEnabled() is TRUE, the event counters and PMCCNTR are not affected by this field.

Otherwise, this field affects the operation of all event counters in Secure state, and if PMCR.DP is 1, the operation of PMCCNTR in Secure state. When PMCR.DP is 0, PMCCNTR is not affected by this field.

If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.

Otherwise:

Bit [16]

SPD, bits [15:14]

AArch32 Secure self-hosted Privileged Debug. Enables or disables debug exceptions from EL3, other than Breakpoint Instruction exceptions.

SPD	Meaning
0b00	Legacy mode. Debug exceptions from EL3 are enabled by the authentication interface.
0b10	Secure privileged debug disabled. Debug exceptions from EL3 are disabled.
0b11	Secure privileged debug enabled. Debug exceptions from EL3 are enabled.

Other values are reserved, and have the CONSTRAINED UNPREDICTABLE behavior that they must have the same behavior as 0b00. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.

This field has no effect on Breakpoint Instruction exceptions. These are always enabled.

This field is ignored in Non-secure state.

If debug exceptions from EL3 are enabled, then debug exceptions from Secure EL0 are also enabled.

Otherwise, debug exceptions from Secure EL0 are enabled only if the value of SDER.SUIDEN is 1.

If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 0b11.

The reset behavior of this field is:

On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.

Bits [13:0]

Accessing SDCR

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b0001	0b0011	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && IsCurrentSecurityState(SS_Secure) then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif !ELUsingAArch32(EL3) && IsCurrentSecurityState(SS_Secure) then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then R[t] = SDCR;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b0001	0b0011	0b001

SDCR, Secure Debug Control Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:29]

MTPME, bit [28]
When FEAT_MTPMU is implemented:

Otherwise:

TDCC, bit [27]
When FEAT_FGT is implemented:

Otherwise:

Bits [26:24]

SCCD, bit [23]
When FEAT_PMUv3p5 is implemented:

Otherwise:

Bit [22]

EPMAD, bit [21]
When FEAT_Debugv8p4 is implemented and FEAT_PMUv3 is implemented:

When FEAT_PMUv3 is implemented:

Otherwise:

EDAD, bit [20]
When FEAT_Debugv8p4 is implemented:

When FEAT_Debugv8p2 is implemented:

Otherwise:

TTRF, bit [19]
When FEAT_TRF is implemented:

Otherwise:

STE, bit [18]
When FEAT_TRF is implemented:

Otherwise:

SPME, bit [17]
When FEAT_PMUv3 is implemented and FEAT_Debugv8p2 is implemented:

When FEAT_PMUv3 is implemented:

Otherwise:

Bit [16]

SPD, bits [15:14]

Bits [13:0]

Accessing SDCR

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0			MTPME	TDCC	RES0			SCCD	RES0	EPMAD	EDAD	TTRF	STE	SPME	RES0	SPD		RES0

SDCR, Secure Debug Control Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:29]

MTPME, bit [28]When FEAT_MTPMU is implemented:

Otherwise:

TDCC, bit [27]When FEAT_FGT is implemented:

Otherwise:

Bits [26:24]

SCCD, bit [23]When FEAT_PMUv3p5 is implemented:

Otherwise:

Bit [22]

EPMAD, bit [21]When FEAT_Debugv8p4 is implemented and FEAT_PMUv3 is implemented:

When FEAT_PMUv3 is implemented:

Otherwise:

EDAD, bit [20]When FEAT_Debugv8p4 is implemented:

When FEAT_Debugv8p2 is implemented:

Otherwise:

TTRF, bit [19]When FEAT_TRF is implemented:

Otherwise:

STE, bit [18]When FEAT_TRF is implemented:

Otherwise:

SPME, bit [17]When FEAT_PMUv3 is implemented and FEAT_Debugv8p2 is implemented:

When FEAT_PMUv3 is implemented:

Otherwise:

Bit [16]

SPD, bits [15:14]

Bits [13:0]

Accessing SDCR

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

MTPME, bit [28]
When FEAT_MTPMU is implemented:

TDCC, bit [27]
When FEAT_FGT is implemented:

SCCD, bit [23]
When FEAT_PMUv3p5 is implemented:

EPMAD, bit [21]
When FEAT_Debugv8p4 is implemented and FEAT_PMUv3 is implemented:

EDAD, bit [20]
When FEAT_Debugv8p4 is implemented:

TTRF, bit [19]
When FEAT_TRF is implemented:

STE, bit [18]
When FEAT_TRF is implemented:

SPME, bit [17]
When FEAT_PMUv3 is implemented and FEAT_Debugv8p2 is implemented: