AT S12E1R, Address Translate Stages 1 and 2 EL1 Read

The AT S12E1R characteristics are:

Purpose

Performs stage 1 and 2 address translation, with permissions as if reading from the given virtual address from EL1, or from EL2 if the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, using the following translation regime:

When FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS} is a reserved value, this instruction is UNDEFINED at EL3.

Configuration

There are no configuration notes.

Attributes

AT S12E1R is a 64-bit System instruction.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Input address for translation
Input address for translation

Bits [63:0]

Input address for translation. The resulting address can be read from the PAR_EL1.

If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.

Executing AT S12E1R

Accesses to this instruction use the following encodings in the System instruction encoding space:

AT S12E1R, <Xt>

op0op1CRnCRmop2
0b010b1000b01110b10000b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL0) || HCR_EL2.<DC,VM> == '00' then AArch64.AT(X[t, 64], TranslationStage_1, EL1, ATAccess_Read); else AArch64.AT(X[t, 64], TranslationStage_12, EL1, ATAccess_Read); elsif PSTATE.EL == EL3 then if !EL2Enabled() then AArch64.AT(X[t, 64], TranslationStage_1, EL1, ATAccess_Read); elsif EL2Enabled() && (ELIsInHost(EL0) || HCR_EL2.<DC,VM> == '00') then AArch64.AT(X[t, 64], TranslationStage_1, EL1, ATAccess_Read); else AArch64.AT(X[t, 64], TranslationStage_12, EL1, ATAccess_Read);


26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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