CNTP_CVAL

AArch64 System register CNTP_CVAL_EL0 bits [63:0] are architecturally mapped to AArch32 System register CNTP_CVAL[63:0].

Attributes

Field descriptions

CompareValue, bits [63:0]

Holds the EL1 physical timer CompareValue.

When CNTP_CTL_EL0.ENABLE is 1, and TimerConditionMet is TRUE for the EL1 physical timer, the timer condition is met and all of the following are true:

CNTP_CTL_EL0.ISTATUS is set to 1.
If CNTP_CTL_EL0.IMASK is 0, an interrupt is generated.

TimerConditionMet is defined by 'Operation of the CompareValue views of the timers'.

The CompareValue view of the timer acts like a 64-bit upcounter timer.

When CNTP_CTL_EL0.ENABLE is 0, the timer condition is not met, but CNTPCT_EL0 continues to count.

If the Generic counter is implemented at a size less than 64 bits, then this field is permitted to be implemented at the same width as the counter, and the upper bits are RES0.

The value of this field is treated as zero-extended in all counter calculations.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing CNTP_CVAL_EL0

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name CNTP_CVAL_EL0 or CNTP_CVAL_EL02 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, CNTP_CVAL_EL0

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b0010	0b010

if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then X[t, 64] = CNTHPS_CVAL_EL2; elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then X[t, 64] = CNTHP_CVAL_EL2; else X[t, 64] = CNTP_CVAL_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x178]; else X[t, 64] = CNTP_CVAL_EL0; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then X[t, 64] = CNTHPS_CVAL_EL2; elsif ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure) then X[t, 64] = CNTHP_CVAL_EL2; else X[t, 64] = CNTP_CVAL_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = CNTP_CVAL_EL0;

MSR CNTP_CVAL_EL0, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b0010	0b010

if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CVAL_EL2 = X[t, 64]; elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CVAL_EL2 = X[t, 64]; else CNTP_CVAL_EL0 = X[t, 64]; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x178] = X[t, 64]; else CNTP_CVAL_EL0 = X[t, 64]; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CVAL_EL2 = X[t, 64]; elsif ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CVAL_EL2 = X[t, 64]; else CNTP_CVAL_EL0 = X[t, 64]; elsif PSTATE.EL == EL3 then CNTP_CVAL_EL0 = X[t, 64];

MRS <Xt>, CNTP_CVAL_EL02

op0	op1	CRn	CRm	op2
0b11	0b101	0b1110	0b0010	0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then if EL2Enabled() && !ELIsInHost(EL0) && CNTHCTL_EL2.EL1NVPCT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = NVMem[0x178]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X[t, 64] = CNTP_CVAL_EL0; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X[t, 64] = CNTP_CVAL_EL0; else UNDEFINED;

MSR CNTP_CVAL_EL02, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b101	0b1110	0b0010	0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then if EL2Enabled() && !ELIsInHost(EL0) && CNTHCTL_EL2.EL1NVPCT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else NVMem[0x178] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then CNTP_CVAL_EL0 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then CNTP_CVAL_EL0 = X[t, 64]; else UNDEFINED;

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CompareValue
CompareValue

CNTP_CVAL_EL0, Counter-timer Physical Timer CompareValue Register

Purpose

Configuration