CNTPCTSS

AArch64 System register CNTPCTSS_EL0 bits [63:0] are architecturally mapped to AArch32 System register CNTPCTSS[63:0].

This register is present only when FEAT_ECV is implemented. Otherwise, direct accesses to CNTPCTSS_EL0 are UNDEFINED.

All reads to the CNTPCTSS_EL0 occur in program order relative to reads to CNTPCT_EL0 or CNTPCTSS_EL0.

This register is a self-synchronised view of the CNTPCT_EL0 counter, and cannot be read speculatively.

Attributes

Field descriptions

Physical count value.

If the access is not trapped and all of the following are true, then reads of CNTPCTSS_EL0 from EL0 or EL1 return (PhysicalCountInt<63:0> - CNTPOFF_EL2<63:0>):

EL2 is implemented and enabled in the current Security state.
CNTHCTL_EL2.ECV is 1.
SCR_EL3.ECVEn is 1.
The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}.

Otherwise, reads of CNTPCTSS_EL0 return PhysicalCountInt<63:0>.

PhysicalCountInt is defined by 'The Physical Counter'.

Bits [63:0]

Accessing CNTPCTSS_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, CNTPCTSS_EL0

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b0000	0b101

if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PCTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PCTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PCTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else if IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' && !ELIsInHost(EL0) then X[t, 64] = PhysicalCountInt() - CNTPOFF_EL2; else X[t, 64] = PhysicalCountInt(); elsif PSTATE.EL == EL1 then if EL2Enabled() && CNTHCTL_EL2.EL1PCTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else if IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' then X[t, 64] = PhysicalCountInt() - CNTPOFF_EL2; else X[t, 64] = PhysicalCountInt(); elsif PSTATE.EL == EL2 then X[t, 64] = PhysicalCountInt(); elsif PSTATE.EL == EL3 then X[t, 64] = PhysicalCountInt();

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Self-synchronized physical count value
Self-synchronized physical count value

CNTPCTSS_EL0, Counter-timer Self-Synchronized Physical Count Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:0]

Accessing CNTPCTSS_EL0

MRS <Xt>, CNTPCTSS_EL0