DISR_EL1

AArch64 System register DISR_EL1 bits [31:0] are architecturally mapped to AArch32 System register DISR[31:0].

This register is present only when FEAT_RAS is implemented. Otherwise, direct accesses to DISR_EL1 are UNDEFINED.

Attributes

Field descriptions

When DISR_EL1.IDS == 0:

Bits [63:32]

A, bit [31]

Set to 1 when an ESB instruction defers an asynchronous SError exception. If the implementation does not include any sources of SError exception that can be synchronized by an Error Synchronization Barrier, then this bit is RES0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [30:25]

IDS, bit [24]

Bits [23:18]

IDS	Meaning
0b0	Deferred error uses architecturally-defined format.

WU, bits [17:16]
When FEAT_RASv2 is implemented:

Otherwise:

Bits [15:13]

AET, bits [12:10]

EA, bit [9]

Bit [8]

WnRV, bit [7]
When FEAT_RASv2 is implemented:

Otherwise:

WnR, bit [6]
When FEAT_RASv2 is implemented:

Otherwise:

DFSC, bits [5:0]

When DISR_EL1.IDS == 1:

Bits [63:32]

A, bit [31]

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [30:25]

IDS, bit [24]

ISS, bits [23:0]

IDS	Meaning
0b1	Deferred error uses IMPLEMENTATION DEFINED format.

Accessing DISR_EL1

An indirect write to DISR_EL1 made by an ESB instruction does not require an explicit synchronization operation for the value that is written to be observed by a direct read of DISR_EL1 occurring in program order after the ESB instruction.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, DISR_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b1100	0b0001	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2.AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2.TMEA == '1')) then X[t, 64] = VDISR_EL2; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && SCR_EL3.EnDSE == '1' then X[t, 64] = VDISR_EL3; elsif HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then X[t, 64] = Zeros(64); else X[t, 64] = DISR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && SCR_EL3.EnDSE == '1' then X[t, 64] = VDISR_EL3; elsif HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then X[t, 64] = Zeros(64); else X[t, 64] = DISR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = DISR_EL1;

MSR DISR_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b1100	0b0001	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2.AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2.TMEA == '1')) then VDISR_EL2 = X[t, 64]; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && SCR_EL3.EnDSE == '1' then VDISR_EL3 = X[t, 64]; elsif HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then return; else DISR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && SCR_EL3.EnDSE == '1' then VDISR_EL3 = X[t, 64]; elsif HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then return; else DISR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then DISR_EL1 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
A	RES0						IDS	RES0						WU		RES0			AET			EA	RES0	WnRV	WnR	DFSC

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
A	RES0						IDS	ISS

DISR_EL1, Deferred Interrupt Status Register

Purpose

Configuration

Attributes

Field descriptions

When DISR_EL1.IDS == 0:

Bits [63:32]

A, bit [31]

Bits [30:25]

IDS, bit [24]

Bits [23:18]

WU, bits [17:16]
When FEAT_RASv2 is implemented:

Otherwise:

Bits [15:13]

AET, bits [12:10]

EA, bit [9]

Bit [8]

WnRV, bit [7]
When FEAT_RASv2 is implemented:

Otherwise:

WnR, bit [6]
When FEAT_RASv2 is implemented:

Otherwise:

DFSC, bits [5:0]

When DISR_EL1.IDS == 1:

Bits [63:32]

A, bit [31]

Bits [30:25]

IDS, bit [24]

ISS, bits [23:0]

Accessing DISR_EL1

MRS <Xt>, DISR_EL1

MSR DISR_EL1, <Xt>

DISR_EL1, Deferred Interrupt Status Register

Purpose

Configuration

Attributes

Field descriptions

When DISR_EL1.IDS == 0:

Bits [63:32]

A, bit [31]

Bits [30:25]

IDS, bit [24]

Bits [23:18]

WU, bits [17:16]When FEAT_RASv2 is implemented:

Otherwise:

Bits [15:13]

AET, bits [12:10]

EA, bit [9]

Bit [8]

WnRV, bit [7]When FEAT_RASv2 is implemented:

Otherwise:

WnR, bit [6]When FEAT_RASv2 is implemented:

Otherwise:

DFSC, bits [5:0]

When DISR_EL1.IDS == 1:

Bits [63:32]

A, bit [31]

Bits [30:25]

IDS, bit [24]

ISS, bits [23:0]

Accessing DISR_EL1

MRS <Xt>, DISR_EL1

MSR DISR_EL1, <Xt>

WU, bits [17:16]
When FEAT_RASv2 is implemented:

WnRV, bit [7]
When FEAT_RASv2 is implemented:

WnR, bit [6]
When FEAT_RASv2 is implemented: