DIT

This register is present only when FEAT_DIT is implemented. Otherwise, direct accesses to DIT are UNDEFINED.

Attributes

Field descriptions

Bits [63:25]

DIT, bit [24]

Data Independent Timing.

DIT	Meaning
0b0	The architecture makes no statement about the timing properties of any instructions.
0b1	The architecture requires that: The timing of every load and store instruction is insensitive to the value of the data being loaded or stored. For certain data processing instructions, the instruction takes a time which is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. For certain data processing instructions, the response of the instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags.

DIT

Meaning

0b0

The architecture makes no statement about the timing properties of any instructions.

0b1

The architecture requires that:

The timing of every load and store instruction is insensitive to the value of the data being loaded or stored.
For certain data processing instructions, the instruction takes a time which is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
For certain data processing instructions, the response of the instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

The Operational Information section of a data processing instruction description indicates if that instruction is affected by this bit.

Note

The architecture makes no statement about the timing properties when the PSTATE.DIT bit is not set. However, it is likely that many of these instructions have timing that is invariant of the data in many situations.

In particular, Arm strongly recommends that the Armv8.3 pointer authentication instructions do not have their timing dependent on the key value used in the pointer authentication in all cases, regardless of the PSTATE.DIT bit.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Bits [23:0]

Accessing DIT

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, DIT

op0	op1	CRn	CRm	op2
0b11	0b011	0b0100	0b0010	0b101

if PSTATE.EL == EL0 then X[t, 64] = Zeros(39):PSTATE.DIT:Zeros(24); elsif PSTATE.EL == EL1 then X[t, 64] = Zeros(39):PSTATE.DIT:Zeros(24); elsif PSTATE.EL == EL2 then X[t, 64] = Zeros(39):PSTATE.DIT:Zeros(24); elsif PSTATE.EL == EL3 then X[t, 64] = Zeros(39):PSTATE.DIT:Zeros(24);

MSR DIT, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b011	0b0100	0b0010	0b101

if PSTATE.EL == EL0 then PSTATE.DIT = X[t, 64]<24>; elsif PSTATE.EL == EL1 then PSTATE.DIT = X[t, 64]<24>; elsif PSTATE.EL == EL2 then PSTATE.DIT = X[t, 64]<24>; elsif PSTATE.EL == EL3 then PSTATE.DIT = X[t, 64]<24>;

MSR DIT, #<imm>

op0	op1	CRn	op2
0b00	0b011	0b0100	0b010

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0							DIT	RES0

DIT, Data Independent Timing

Purpose

Configuration