GCSCR_EL3

This register is present only when FEAT_GCS is implemented and EL3 is implemented. Otherwise, direct accesses to GCSCR_EL3 are UNDEFINED.

Attributes

Field descriptions

Bits [63:10]

STREn, bit [9]

Execution of the following instructions are trapped:

GCSSTR.
GCSSTTR.

STREn	Meaning
0b0	Execution of any of the specified instructions at EL3 cause a GCS exception.
0b1	This control does not cause any instructions to be trapped.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

PUSHMEn, bit [8]

Trap GCSPUSHM instruction.

PUSHMEn	Meaning
0b0	Execution of a GCSPUSHM instruction at EL3 causes a Trap exception.
0b1	This control does not cause any instructions to be trapped.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Bit [7]

EXLOCKEN, bit [6]

Exception state lock.

Prevents MSR instructions from writing to ELR_EL3 or SPSR_EL3.

EXLOCKEN	Meaning
0b0	EL3 exception state locking disabled.
0b1	EL3 exception state locking enabled.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

RVCHKEN, bit [5]

Return value check enable.

RVCHKEN	Meaning
0b0	Return value checking disabled at EL3.
0b1	Return value checking enabled at EL3.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [4:1]

PCRSEL, bit [0]

Guarded Control Stack procedure call return enable selection.

PCRSEL	Meaning
0b0	Guarded Control Stack at EL3 is not PCR Selected.
0b1	Guarded Control Stack at EL3 is PCR Selected.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Accessing GCSCR_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, GCSCR_EL3

op0	op1	CRn	CRm	op2
0b11	0b110	0b0010	0b0101	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = GCSCR_EL3;

MSR GCSCR_EL3, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b110	0b0010	0b0101	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3.GCSCR_EL3 == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else GCSCR_EL3 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																						STREn	PUSHMEn	RES0	EXLOCKEN	RVCHKEN	RES0				PCRSEL

GCSCR_EL3, Guarded Control Stack Control Register (EL3)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:10]

STREn, bit [9]

PUSHMEn, bit [8]

Bit [7]

EXLOCKEN, bit [6]

RVCHKEN, bit [5]

Bits [4:1]

PCRSEL, bit [0]

Accessing GCSCR_EL3

MRS <Xt>, GCSCR_EL3

MSR GCSCR_EL3, <Xt>