HACDBSCONS

This register is present only when FEAT_HACDBS is implemented. Otherwise, direct accesses to HACDBSCONS_EL2 are UNDEFINED.

Attributes

Field descriptions

ERR_REASON, bits [63:62]

Reason for HACDBS error.

ERR_REASON	Meaning
0b00	The PE has not experienced an error while processing the HACDBS.
0b01	STRUCTF - A read of an entry from the HACDBS has experienced a fault.
0b10	IPAF - A stage 2 walk of an IPA from a HACDBS entry has experienced an MMU fault.
0b11	IPAHACF - An entry from the HACDBS experienced an error that is not an MMU fault.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [61:19]

INDEX, bits [18:0]

Accessing HACDBSCONS_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HACDBSCONS_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0011	0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = NVMem[0x308]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.HACDBSEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.HACDBSEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = HACDBSCONS_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HACDBSCONS_EL2;

MSR HACDBSCONS_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0011	0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem[0x308] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.HACDBSEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.HACDBSEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HACDBSCONS_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HACDBSCONS_EL2 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERR_REASON		RES0
RES0													INDEX

HACDBSCONS_EL2, Hardware Accelerator for Cleaning Dirty State Consumer Register

Purpose

Configuration