HFGRTR2

This register is present only when FEAT_FGT2 is implemented. Otherwise, direct accesses to HFGRTR2_EL2 are UNDEFINED.

Attributes

Field descriptions

Bits [63:3]

nRCWSMASK_EL1, bit [2]
When FEAT_THE is implemented:

Trap MRS or MRRS reads of RCWSMASK_EL1 at EL1 using AArch64 to EL2.

nRCWSMASK_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then unless the read generates a higher priority exception: MRS reads of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRRS reads of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14.
0b1	MRS and MRRS reads of RCWSMASK_EL1 are not trapped by this mechanism.

nRCWSMASK_EL1

Meaning

0b0

If EL2 is implemented and enabled in the current Security state, then unless the read generates a higher priority exception:

MRS reads of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
MRRS reads of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14.

0b1

MRS and MRRS reads of RCWSMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nERXGSR_EL1, bit [1]
When FEAT_RASv2 is implemented:

Trap MRS reads of ERXGSR_EL1 at EL1 using AArch64 to EL2.

nERXGSR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of ERXGSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of ERXGSR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

Accessing this field has the following behavior:

This field is permitted to be RES0 if all of the following are true:
- ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI.
- ERRIDR_EL1.NUM is zero.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nPFAR_EL1, bit [0]
When FEAT_PFAR is implemented:

Trap MRS reads of PFAR_EL1 at EL1 using AArch64 to EL2.

nPFAR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of PFAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of PFAR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Accessing HFGRTR2_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HFGRTR2_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0011	0b0001	0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = NVMem[0x2C0]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FGTEn2 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = HFGRTR2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HFGRTR2_EL2;

MSR HFGRTR2_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0011	0b0001	0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem[0x2C0] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FGTEn2 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HFGRTR2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HFGRTR2_EL2 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
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RES0
RES0																													nRCWSMASK_EL1	nERXGSR_EL1	nPFAR_EL1

HFGRTR2_EL2, Hypervisor Fine-Grained Read Trap Register 2

Purpose

Configuration

Attributes

Field descriptions

Bits [63:3]

nRCWSMASK_EL1, bit [2]
When FEAT_THE is implemented:

Otherwise:

nERXGSR_EL1, bit [1]
When FEAT_RASv2 is implemented:

Otherwise:

nPFAR_EL1, bit [0]
When FEAT_PFAR is implemented:

Otherwise:

Accessing HFGRTR2_EL2

MRS <Xt>, HFGRTR2_EL2

MSR HFGRTR2_EL2, <Xt>

HFGRTR2_EL2, Hypervisor Fine-Grained Read Trap Register 2

Purpose

Configuration

Attributes

Field descriptions

Bits [63:3]

nRCWSMASK_EL1, bit [2]When FEAT_THE is implemented:

Otherwise:

nERXGSR_EL1, bit [1]When FEAT_RASv2 is implemented:

Otherwise:

nPFAR_EL1, bit [0]When FEAT_PFAR is implemented:

Otherwise:

Accessing HFGRTR2_EL2

MRS <Xt>, HFGRTR2_EL2

MSR HFGRTR2_EL2, <Xt>

nRCWSMASK_EL1, bit [2]
When FEAT_THE is implemented:

nERXGSR_EL1, bit [1]
When FEAT_RASv2 is implemented:

nPFAR_EL1, bit [0]
When FEAT_PFAR is implemented: