ID_AA64MMFR4

Provides additional information about implemented memory model and memory management support in AArch64.

Configuration

Attributes

Field descriptions

Bits [63:40]

E3DSE, bits [39:36]

Delegated SError exceptions from EL3. Describes support for delegated SError injection from EL3.

The value of this field is an IMPLEMENTATION DEFINED choice of:

E3DSE	Meaning
0b0000	FEAT_E3DSE is not implemented.
0b0001	FEAT_E3DSE is implemented. The following are implemented: Register fields SCR_EL3.DSE and SCR_EL3.EnDSE. Registers VSESR_EL3 and VDISR_EL3.

E3DSE

Meaning

0b0000

FEAT_E3DSE is not implemented.

0b0001

FEAT_E3DSE is implemented. The following are implemented:

Register fields SCR_EL3.DSE and SCR_EL3.EnDSE.
Registers VSESR_EL3 and VDISR_EL3.

All other values are reserved.

FEAT_E3DSE implements the functionality described by the value 0b0001.

Access to this field is RO.

Bits [35:28]

E2H0, bits [27:24]

Indicates support for programming HCR_EL2.E2H.

The value of this field is an IMPLEMENTATION DEFINED choice of:

E2H0	Meaning
0b0000	FEAT_E2H0 is implemented.
0b1110	FEAT_E2H0 is not implemented. HCR_EL2.NV1 is RAZ/WI.
0b1111	FEAT_E2H0 is not implemented.

All other values are reserved.

If FEAT_NV is not implemented, then the value 0b1110 is not permitted.

If FEAT_E2H0 is implemented and FEAT_VHE is not implemented, then HCR_EL2.E2H is RES0.

If FEAT_E2H0 is implemented and FEAT_VHE is implemented, then HCR_EL2.E2H can be programmed to 0 or 1.

If FEAT_E2H0 is not implemented then:

FEAT_VHE is implemented.
HCR_EL2.E2H is RAO, and behaves as though it is 1.

Access to this field is RO.

NV_frac, bits [23:20]

Indicates support for a subset of FEAT_NV and FEAT_NV2 behaviors.

The value of this field is an IMPLEMENTATION DEFINED choice of:

NV_frac	Meaning
0b0000	Support for FEAT_NV and FEAT_NV2 is described in ID_AA64MMFR2_EL1.NV.
0b0001	FEAT_NV and FEAT_NV2 are implemented, but all of the following apply: ID_AA64MMFR2_EL1.NV is 0b0000. Programming HCR_EL2.{NV, NV2} to {1, 0} behaves as {1, 1}.

NV_frac

Meaning

0b0000

Support for FEAT_NV and FEAT_NV2 is described in ID_AA64MMFR2_EL1.NV.

0b0001

FEAT_NV and FEAT_NV2 are implemented, but all of the following apply:

ID_AA64MMFR2_EL1.NV is 0b0000.
Programming HCR_EL2.{NV, NV2} to {1, 0} behaves as {1, 1}.

Access to this field is RO.

FGWTE3, bits [19:16]

Indicates support for Fine Grained Write Trap EL3 feature.

The value of this field is an IMPLEMENTATION DEFINED choice of:

FGWTE3	Meaning
0b0000	Fine Grained Write Trap EL3 is not supported.
0b0001	Fine Grained Write Trap EL3 is supported.

All other values are reserved.

FEAT_FGWTE3 implements the functionality identified by the value 0b0001.

Access to this field is RO.

HACDBS, bits [15:12]

Support for Hardware accelerator for cleaning Dirty state.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HACDBS	Meaning
0b0000	Hardware accelerator for cleaning Dirty state is not supported.
0b0001	Hardware accelerator for cleaning Dirty state is supported.

All other values are reserved.

FEAT_HACDBS implements the functionality identified by the value 0b0001.

Access to this field is RO.

ASID2, bits [11:8]

Indicates support for concurrent use of two ASIDs.

The value of this field is an IMPLEMENTATION DEFINED choice of:

ASID2	Meaning
0b0000	FEAT_ASID2 is not implemented.
0b0001	FEAT_ASID2 is implemented.

All other values are reserved.

From Armv9.5, the value 0b0000 is not permitted.

Access to this field is RO.

EIESB, bits [7:4]
When FEAT_IESB is implemented:

Early Implicit Error Synchronization event. Indicates whether the implicit Error synchronization event inserted on taking an exception to ELx when SCTLR_ELx.IESB is 1 is inserted before or after the exception is taken.

The value of this field is an IMPLEMENTATION DEFINED choice of:

EIESB	Meaning
0b1111	FEAT_IESB is implemented. When SError exceptions are routed to EL3, and either FEAT_DoubleFault is not implemented or the Effective value of SCR_EL3.NMEA is 1, an implicit Error synchronization event might be inserted after an exception is taken to EL3.
0b0000	FEAT_IESB is not implemented, or behavior is not described.
0b0001	FEAT_IESB is implemented. When SError exceptions are routed to EL3, and either FEAT_DoubleFault is not implemented or the Effective value of SCR_EL3.NMEA is 1, an implicit Error synchronization event is inserted before an exception taken to EL3.
0b0010	As 0b0001, and also: When SError exceptions are routed to EL1, and either FEAT_DoubleFault2 is not implemented or the Effective value of SCTLR2_EL1.NMEA is 1, an implicit Error synchronization event is inserted before an exception taken to EL1. When SError exceptions are routed to EL2, and either FEAT_DoubleFault2 is not implemented or the Effective value of SCTLR2_EL2.NMEA is 1, an implicit Error synchronization event is inserted before an exception taken to EL2.

All other values are reserved.

This field describes the PE behavior on taking an exception to ELx when SCTLR_ELx.IESB is 1. This field does not describe the behavior when SCTLR_ELx.IESB is 0.

The behavior described by this field only applies for the conditions described above. For example, if ID_AA64MMFR4_EL1.EIESB reads as 0b0001, then it does not describe the behavior when SError exceptions are not routed to EL3, or when FEAT_DoubleFault is implemented and the Effective value of SCR_EL3.NMEA is 0.

Inserting the event before the exception is taken means that if the Error synchronization event causes an SError exception to become pending, and SError exceptions are not masked and not disabled, then the SError exception is taken in place of the original exception.

When FEAT_IESB is not implemented, the only permitted value of this field is 0b0000.

Access to this field is RO.

Otherwise:

Bits [3:0]

Accessing ID_AA64MMFR4_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ID_AA64MMFR4_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0000	0b0111	0b100

if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64MMFR4_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64MMFR4_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_AA64MMFR4_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_AA64MMFR4_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64MMFR4_EL1;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								E3DSE				RES0
RES0				E2H0				NV_frac				FGWTE3				HACDBS				ASID2				EIESB				RES0

ID_AA64MMFR4_EL1, AArch64 Memory Model Feature Register 4

Purpose

Configuration

Attributes

Field descriptions

Bits [63:40]

E3DSE, bits [39:36]

Bits [35:28]

E2H0, bits [27:24]

NV_frac, bits [23:20]

FGWTE3, bits [19:16]

HACDBS, bits [15:12]

ASID2, bits [11:8]

EIESB, bits [7:4]
When FEAT_IESB is implemented:

Otherwise:

Bits [3:0]

Accessing ID_AA64MMFR4_EL1

MRS <Xt>, ID_AA64MMFR4_EL1

ID_AA64MMFR4_EL1, AArch64 Memory Model Feature Register 4

Purpose

Configuration

Attributes

Field descriptions

Bits [63:40]

E3DSE, bits [39:36]

Bits [35:28]

E2H0, bits [27:24]

NV_frac, bits [23:20]

FGWTE3, bits [19:16]

HACDBS, bits [15:12]

ASID2, bits [11:8]

EIESB, bits [7:4]When FEAT_IESB is implemented:

Otherwise:

Bits [3:0]

Accessing ID_AA64MMFR4_EL1

MRS <Xt>, ID_AA64MMFR4_EL1

EIESB, bits [7:4]
When FEAT_IESB is implemented: