ISR_EL1

When FEAT_NMI is implemented, also shows whether a pending IRQ or FIQ interrupt has Superpriority.

Configuration

AArch64 System register ISR_EL1 bits [31:0] are architecturally mapped to AArch32 System register ISR[31:0].

Attributes

Field descriptions

Bits [63:11]

IS, bit [10]
When FEAT_NMI is implemented:

IRQ with Superpriority pending bit. Indicates whether an IRQ interrupt with Superpriority is pending.

IS	Meaning
0b0	No pending IRQ with Superpriority.
0b1	An IRQ interrupt with Superpriority is pending.

If all of the following apply then this field shows the pending status of virtual IRQ interrupts with Superpriority:

EL2 is implemented and enabled in the current Security state.
HCR_EL2.IMO is 1.
The PE is executing at EL1.

Otherwise, this field shows the pending status of physical IRQ interrupts with Superpriority.

Otherwise:

FS, bit [9]
When FEAT_NMI is implemented:

FIQ with Superpriority pending bit. Indicates whether an FIQ interrupt with Superpriority is pending.

FS	Meaning
0b0	No pending FIQ with Superpriority.
0b1	An FIQ interrupt with Superpriority is pending.

If all of the following apply then this field shows the pending status of virtual FIQ interrupts with Superpriority:

EL2 is implemented and enabled in the current Security state.
HCR_EL2.FMO is 1.
The PE is executing at EL1.

Otherwise, this field shows the pending status of physical FIQ interrupts with Superpriority.

Otherwise:

A, bit [8]

SError exception pending bit. Indicates whether an SError exception is pending.

A	Meaning
0b0	No pending SError.
0b1	An SError exception is pending.

If all of the following apply then this field shows the pending status of virtual SError exceptions:

EL2 is implemented and enabled in the current Security state.
Any of the following apply:
- HCR_EL2.AMO is 1.
- FEAT_DoubleFault2 is implemented and the Effective value of HCRX_EL2.TMEA is 1.
The PE is executing at EL1.

Otherwise, when FEAT_E3DSE is implemented and SCR_EL3.EnDSE is 1, this field shows the pending status of delegated SError exceptions at EL2 and EL1.

Otherwise, this field shows the pending status of physical SError exceptions.

If the physical SError exception is edge-triggered, this field is cleared to zero when the physical SError exception is taken.

I, bit [7]

IRQ pending bit. Indicates whether an IRQ interrupt is pending.

I	Meaning
0b0	No pending IRQ.
0b1	An IRQ interrupt is pending.

If all of the following apply then this field shows the pending status of virtual IRQ interrupts:

EL2 is implemented and enabled in the current Security state.
HCR_EL2.IMO is 1.
The PE is executing at EL1.

Otherwise, this field shows the pending status of physical IRQ interrupts.

Note

This bit indicates the presence of a pending IRQ interrupt regardless of whether the interrupt has Superpriority.

F, bit [6]

FIQ pending bit. Indicates whether an FIQ interrupt is pending.

F	Meaning
0b0	No pending FIQ.
0b1	An FIQ interrupt is pending.

If all of the following apply then this field shows the pending status of virtual FIQ interrupts:

EL2 is implemented and enabled in the current Security state.
HCR_EL2.FMO is 1.
The PE is executing at EL1.

Otherwise, this field shows the pending status of physical FIQ interrupts.

Note

This bit indicates the presence of a pending FIQ interrupt regardless of whether the interrupt has Superpriority.

Bits [5:0]

Accessing ISR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ISR_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b1100	0b0001	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.ISR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ISR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ISR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ISR_EL1;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																					IS	FS	A	I	F	RES0

ISR_EL1, Interrupt Status Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:11]

IS, bit [10]
When FEAT_NMI is implemented:

Otherwise:

FS, bit [9]
When FEAT_NMI is implemented:

Otherwise:

A, bit [8]

I, bit [7]

F, bit [6]

Bits [5:0]

Accessing ISR_EL1

MRS <Xt>, ISR_EL1

ISR_EL1, Interrupt Status Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:11]

IS, bit [10]When FEAT_NMI is implemented:

Otherwise:

FS, bit [9]When FEAT_NMI is implemented:

Otherwise:

A, bit [8]

I, bit [7]

F, bit [6]

Bits [5:0]

Accessing ISR_EL1

MRS <Xt>, ISR_EL1

IS, bit [10]
When FEAT_NMI is implemented:

FS, bit [9]
When FEAT_NMI is implemented: