MAIR2_EL3, Extended Memory Attribute Indirection Register (EL3)

The MAIR2_EL3 characteristics are:

Purpose

Provides the memory attribute encodings corresponding to the possible AttrIndx values in a VMSAv8-64 or VMSAv9-128 translation table entry for stage 1 translations at EL1.

Configuration

This register is present only when FEAT_AIE is implemented. Otherwise, direct accesses to MAIR2_EL3 are UNDEFINED.

Attributes

MAIR2_EL3 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Attr7Attr6Attr5Attr4
Attr3Attr2Attr1Attr0

Attr<n>, bits [8n+7:8n], for n = 7 to 0

Memory Attribute encoding.

When stage 1 Attributes Index Extension is enabled and AttrIndx[3] in a VMSAv8-64 or VMSAv9-128 translation table entry is 1, AttrIndx[2:0] gives the value of <n> in Attr<n>.

When stage 1 Attributes Index Extension is enabled and AttrIndx[3] in a VMSAv8-64 or VMSAv9-128 translation table entry is 0, see MAIR_ELx.Attr

Attr is encoded as follows:

AttrMeaning
0b0000dd00Device memory. See encoding of 'dd' for the type of Device memory.
0b0000dd01If FEAT_XS is implemented: Device memory with the XS attribute set to 0. See encoding of 'dd' for the type of Device memory. Otherwise, UNPREDICTABLE.
0b0000dd1xUNPREDICTABLE.
0booooiiii, (oooo != 0000 and iiii != 0000)Normal memory. See encoding of 'oooo' and 'iiii' for the type of Normal Memory.
0b01000000If FEAT_XS is implemented: Normal Inner Non-cacheable, Outer Non-cacheable memory with the XS attribute set to 0. Otherwise, UNPREDICTABLE.
0b10100000If FEAT_XS is implemented: Normal Inner Write-through Cacheable, Outer Write-through Cacheable, Read-Allocate, No-Write Allocate, Non-transient memory with the XS attribute set to 0. Otherwise, UNPREDICTABLE.
0b11110000If FEAT_MTE2 is implemented: Tagged Normal Inner Write-Back, Outer Write-Back, Read-Allocate, Write-Allocate Non-transient memory. Otherwise, UNPREDICTABLE.
0bxxxx0000, where xxxx != 0000 and xxxx != 0100 and xxxx != 1010 and xxxx != 1111UNPREDICTABLE.

'dd' is encoded as follows:

ddMeaning
0b00Device-nGnRnE memory
0b01Device-nGnRE memory
0b10Device-nGRE memory
0b11Device-GRE memory

'oooo' is encoded as follows:

'oooo'Meaning
0b0000See encoding of Attr
0b00RW, RW not 0b00Normal memory, Outer Write-Through Transient
0b0100Normal memory, Outer Non-cacheable
0b01RW, RW not 0b00Normal memory, Outer Write-Back Transient
0b10RWNormal memory, Outer Write-Through Non-transient
0b11RWNormal memory, Outer Write-Back Non-transient

R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.

'iiii' is encoded as follows:

'iiii'Meaning
0b0000See encoding of Attr
0b00RW, RW not 0b00Normal memory, Inner Write-Through Transient
0b0100Normal memory, Inner Non-cacheable
0b01RW, RW not 0b00Normal memory, Inner Write-Back Transient
0b10RWNormal memory, Inner Write-Through Non-transient
0b11RWNormal memory, Inner Write-Back Non-transient

R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.

The R and W bits in 'oooo' and 'iiii' fields have the following meanings:

R or WMeaning
0b0No Allocate
0b1Allocate

When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.

The reset behavior of this field is:

Accessing MAIR2_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MAIR2_EL3

op0op1CRnCRmop2
0b110b1100b10100b00010b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = MAIR2_EL3;

MSR MAIR2_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b10100b00010b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3.MAIR2_EL3 == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else MAIR2_EL3 = X[t, 64];


26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.