MFAR_EL3

Records the faulting physical address for a Granule Protection Check, synchronous External abort, or SError exception taken to EL3.

Configuration

This register is present only when FEAT_PFAR is implemented or FEAT_RME is implemented. Otherwise, direct accesses to MFAR_EL3 are UNDEFINED.

Attributes

Field descriptions

When FEAT_RME is implemented and the exception is a GPC exception:

NS, bit [63]

Together with MFAR_EL3.NSE, reports the physical address space of the access that triggered the exception.

NSE	NS	Meaning
0b0	0b0	When Secure state is implemented, Secure. Otherwise reserved.
0b0	0b1	Non-secure.
0b1	0b0	Root.
0b1	0b1	Realm.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

NSE, bit [62]

Together with MFAR_EL3.NS, reports the physical address space of the access that triggered the exception.

For a description of the values derived by evaluating NS and NSE together, see MFAR_EL3.NS.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [61:56]

FPA[55:52], bits [55:52]
When FEAT_D128 is implemented:

When FEAT_D128 is implemented, extension to MFAR_EL3.FPA[47:12].

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

FPA[51:48], bits [51:48]
When FEAT_LPA is implemented:

When FEAT_LPA is implemented, extension to MFAR_EL3.FPA[47:12].

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

FPA, bits [47:12]

Bits [47:12] of the Faulting Physical Address.

For implementations with fewer than 48 physical address bits, the corresponding upper bits in this field are RES0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [11:0]

When FEAT_PFAR is implemented and the exception is a synchronous External abort or SError exception:

NS, bit [63]
When FEAT_RME is implemented:

Together with MFAR_EL3.NSE, reports the physical address space of the access that triggered the exception.

NSE	NS	Meaning
0b0	0b0	When Secure state is implemented, Secure. Otherwise reserved.
0b0	0b1	Non-secure.
0b1	0b0	Root.
0b1	0b1	Realm.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Non-secure. Reports the physical address space of the access that triggered the exception.

NS	Meaning
0b0	Secure physical address space.
0b1	Non-secure physical address space.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

NSE, bit [62]
When FEAT_RME is implemented:

Together with MFAR_EL3.NS, reports the physical address space of the access that triggered the exception.

For a description of the values derived by evaluating NS and NSE together, see MFAR_EL3.NS.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [61:56]

PA[55:52], bits [55:52]
When FEAT_D128 is implemented:

When FEAT_D128 is implemented, extension to MFAR_EL3.PA[47:0].

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

PA[51:48], bits [51:48]
When FEAT_LPA is implemented:

When FEAT_LPA is implemented, extension to MFAR_EL3.PA[47:0].

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

PA, bits [47:0]

Physical Address. Bits [47:0] of the aborting physical address.

For implementations with fewer than 48 physical address bits, the corresponding upper bits in this field are RES0.

The recorded address can be any address within the same naturally-aligned fault granule as the faulting physical address, where the size of the fault granule is IMPLEMENTATION DEFINED and no larger than the larger than:

The size of the range of values permitted to be recorded in FAR_EL3.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing MFAR_EL3

MFAR_EL3 is not valid and reads UNKNOWN if ESR_EL3.EC is recorded indicating an Abort or SError exception and ESR_EL3.PFV is recorded as 0.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MFAR_EL3

op0	op1	CRn	CRm	op2
0b11	0b110	0b0110	0b0000	0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = MFAR_EL3;

MSR MFAR_EL3, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b110	0b0110	0b0000	0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then MFAR_EL3 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NS	NSE	RES0						FPA[55:52]				FPA[51:48]				FPA
FPA																				RES0

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NS	NSE	RES0						PA[55:52]				PA[51:48]				PA
PA

MFAR_EL3, Physical Fault Address Register (EL3)

Purpose

Configuration

Attributes

Field descriptions

When FEAT_RME is implemented and the exception is a GPC exception:

NS, bit [63]

NSE, bit [62]

Bits [61:56]

FPA[55:52], bits [55:52]
When FEAT_D128 is implemented:

Otherwise:

FPA[51:48], bits [51:48]
When FEAT_LPA is implemented:

Otherwise:

FPA, bits [47:12]

Bits [11:0]

When FEAT_PFAR is implemented and the exception is a synchronous External abort or SError exception:

NS, bit [63]
When FEAT_RME is implemented:

Otherwise:

NSE, bit [62]
When FEAT_RME is implemented:

Otherwise:

Bits [61:56]

PA[55:52], bits [55:52]
When FEAT_D128 is implemented:

Otherwise:

PA[51:48], bits [51:48]
When FEAT_LPA is implemented:

Otherwise:

PA, bits [47:0]

Accessing MFAR_EL3

MRS <Xt>, MFAR_EL3

MSR MFAR_EL3, <Xt>

MFAR_EL3, Physical Fault Address Register (EL3)

Purpose

Configuration

Attributes

Field descriptions

When FEAT_RME is implemented and the exception is a GPC exception:

NS, bit [63]

NSE, bit [62]

Bits [61:56]

FPA[55:52], bits [55:52]When FEAT_D128 is implemented:

Otherwise:

FPA[51:48], bits [51:48]When FEAT_LPA is implemented:

Otherwise:

FPA, bits [47:12]

Bits [11:0]

When FEAT_PFAR is implemented and the exception is a synchronous External abort or SError exception:

NS, bit [63]When FEAT_RME is implemented:

Otherwise:

NSE, bit [62]When FEAT_RME is implemented:

Otherwise:

Bits [61:56]

PA[55:52], bits [55:52]When FEAT_D128 is implemented:

Otherwise:

PA[51:48], bits [51:48]When FEAT_LPA is implemented:

Otherwise:

PA, bits [47:0]

Accessing MFAR_EL3

MRS <Xt>, MFAR_EL3

MSR MFAR_EL3, <Xt>

FPA[55:52], bits [55:52]
When FEAT_D128 is implemented:

FPA[51:48], bits [51:48]
When FEAT_LPA is implemented:

NS, bit [63]
When FEAT_RME is implemented:

NSE, bit [62]
When FEAT_RME is implemented:

PA[55:52], bits [55:52]
When FEAT_D128 is implemented:

PA[51:48], bits [51:48]
When FEAT_LPA is implemented: