The MPAM1_EL1 characteristics are:
Holds information to generate MPAM labels for memory requests when executing at EL1.
When EL2 is implemented and enabled in the current Security state, the MPAM virtualization option is present, MPAMHCR_EL2.GSTAPP_PLK == 1 and HCR_EL2.TGE == 0, MPAM1_EL1 is used instead of MPAM0_EL1 to generate MPAM labels for memory requests when executing at EL0.
MPAM1_EL1 is an alias for MPAM2_EL2 when executing at EL2 and the Effective value of HCR_EL2.E2H is 1.
MPAM1_EL12 is an alias for MPAM1_EL1 when executing at EL2 or EL3 and the Effective value of HCR_EL2.E2H is 1.
If EL2 is implemented and enabled in the current Security state, the MPAM virtualization option is present and MPAMHCR_EL2.EL1_VPMEN == 1, MPAM PARTIDs in MPAM1_EL1 are virtual and mapped into physical PARTIDs for the current Security state. This mapping of MPAM1_EL1 virtual PARTIDs to physical PARTIDs when EL1_VPMEN is 1 also applies when MPAM1_EL1 is used at EL0 due to MPAMHCR_EL2.GSTAPP_PLK.
AArch64 System register MPAM1_EL1 bit [63] is architecturally mapped to AArch64 System register MPAM3_EL3[63] when EL3 is implemented.
AArch64 System register MPAM1_EL1 bit [63] is architecturally mapped to AArch64 System register MPAM2_EL2[63] when EL3 is not implemented and EL2 is implemented.
This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAM1_EL1 are UNDEFINED.
MPAM1_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPAMEN | RES0 | FORCED_NS | RES0 | ALTSP_FRCD | RES0 | PMG_D | PMG_I | ||||||||||||||||||||||||
| PARTID_D | PARTID_I | ||||||||||||||||||||||||||||||
MPAM Enable. MPAM is enabled when MPAMEN == 1. When disabled, all PARTIDs and PMGs are output as their default value in the corresponding ID space.
| MPAMEN | Meaning |
|---|---|
| 0b0 |
The default PARTID and default PMG are output in MPAM information. |
| 0b1 |
MPAM information is output based on the MPAMn_ELx register for ELn according the MPAM configuration. |
If EL3 is implemented, this field is read-only and reads the current value of the read/write bit MPAM3_EL3.MPAMEN.
If EL3 is not implemented and EL2 is implemented, this field is read-only and reads the current value of the read/write bit MPAM2_EL2.MPAMEN.
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
In the Secure state, FORCED_NS indicates the state of MPAM3_EL3.FORCE_NS.
| FORCED_NS | Meaning |
|---|---|
| 0b0 | In the Non-secure state, always reads as 0. In the Secure state, indicates that MPAM3_EL3.FORCE_NS == 0. |
| 0b1 |
In the Secure state, indicates that MPAM3_EL3.FORCE_NS == 1. |
Always reads as 0 in the Non-secure state.
Writes are ignored.
Access to this field is RO.
Reserved, RES0.
Reserved, RES0.
Alternative PARTID forced for PARTIDs in this register.
| ALTSP_FRCD | Meaning |
|---|---|
| 0b0 |
The PARTIDs in MPAM1_EL1 and MPAM0_EL1 are using the primary PARTID space. |
| 0b1 |
The PARTIDs in MPAM1_EL1 and MPAM0_EL1 are using the alternative PARTID space. |
This bit indicates that a higher Exception level has forced the PARTIDs in this register to use the alternative PARTID space defined for the current Security state.
In MPAM1_EL1, it also indicates that MPAM0_EL1 is forced to use alternative PARTID space.
For more information, see 'Alternative PARTID spaces and selection'.
Accessing this field has the following behavior:
Reserved, RES0.
Reserved, RES0.
Performance monitoring group property for PARTID_D.
The reset behavior of this field is:
Performance monitoring group property for PARTID_I.
The reset behavior of this field is:
Partition ID for data accesses, including load and store accesses, made from EL1.
The reset behavior of this field is:
Partition ID for instruction accesses made from EL1.
The reset behavior of this field is:
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name MPAM1_EL1 or MPAM1_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.
None of the fields in this register are permitted to be cached in a TLB.
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && MPAM2_EL2.TRAPMPAM1EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x900]; else X[t, 64] = MPAM1_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = MPAM2_EL2; else X[t, 64] = MPAM1_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = MPAM1_EL1;
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && MPAM2_EL2.TRAPMPAM1EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x900] = X[t, 64]; else MPAM1_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then MPAM2_EL2 = X[t, 64]; else MPAM1_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then MPAM1_EL1 = X[t, 64];
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b101 | 0b1010 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X[t, 64] = NVMem[0x900]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = MPAM1_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X[t, 64] = MPAM1_EL1; else UNDEFINED;
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b101 | 0b1010 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem[0x900] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else MPAM1_EL1 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then MPAM1_EL1 = X[t, 64]; else UNDEFINED;
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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