PMCCNTSVR

AArch64 System register PMCCNTSVR_EL1 bits [63:0] are architecturally mapped to External register PMU.PMCCNTSVR_EL1[63:0].

This register is present only when FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMCCNTSVR_EL1 are UNDEFINED.

Attributes

Field descriptions

CCNT, bits [63:0]

Sampled Cycle Count. The value of PMCCNTR_EL0 at the last successful Capture event.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing PMCCNTSVR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMCCNTSVR_EL1

op0	op1	CRn	CRm	op2
0b10	0b000	0b1110	0b1011	0b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPMSS == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HDFGRTR2_EL2.nPMSSDATA == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSS == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMCCNTSVR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPMSS == '0' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.EnPMSS == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMCCNTSVR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMCCNTSVR_EL1;

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CCNT
CCNT

PMCCNTSVR_EL1, Performance Monitors Cycle Count Saved Value Register

Purpose

Configuration

Attributes

Field descriptions

CCNT, bits [63:0]

Accessing PMCCNTSVR_EL1

MRS <Xt>, PMCCNTSVR_EL1