PMICNTSVR

AArch64 System register PMICNTSVR_EL1 bits [63:0] are architecturally mapped to External register PMU.PMICNTSVR_EL1[63:0].

This register is present only when FEAT_PMUv3_ICNTR is implemented and FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMICNTSVR_EL1 are UNDEFINED.

Attributes

Field descriptions

ICNT, bits [63:0]

Sampled Instruction Count. The value of PMICNTR_EL0 at the last successful Capture event.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing PMICNTSVR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMICNTSVR_EL1

op0	op1	CRn	CRm	op2
0b10	0b000	0b1110	0b1100	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPMSS == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HDFGRTR2_EL2.nPMSSDATA == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSS == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMICNTSVR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPMSS == '0' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.EnPMSS == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMICNTSVR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMICNTSVR_EL1;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
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ICNT
ICNT

PMICNTSVR_EL1, Performance Monitors Instruction Count Saved Value Register

Purpose

Configuration

Attributes

Field descriptions

ICNT, bits [63:0]

Accessing PMICNTSVR_EL1

MRS <Xt>, PMICNTSVR_EL1