SVCR

This register is present only when FEAT_SME is implemented. Otherwise, direct accesses to SVCR are UNDEFINED.

Attributes

Field descriptions

Bits [63:2]

ZA, bit [1]

Enables SME ZA storage. If FEAT_SME2 is implemented, also enables SME2 ZT0 storage.

When this storage is disabled, execution of an instruction which can access it is trapped. The exception is reported using an ESR_ELx.{EC, SMTC} value of {0x1D, 0x3}.

The possible values of this bit are:

ZA	Meaning
0b0	SME ZA storage and, if implemented, ZT0 storage are invalid and not accessible. This control causes execution at any Exception level of instructions that can access this storage to be trapped.
0b1	SME ZA storage and, if implemented, ZT0 storage are valid and accessible. This control does not cause execution of any instructions to be trapped.

Meaning

0b0

SME ZA storage and, if implemented, ZT0 storage are invalid and not accessible.

This control causes execution at any Exception level of instructions that can access this storage to be trapped.

0b1

SME ZA storage and, if implemented, ZT0 storage are valid and accessible.

This control does not cause execution of any instructions to be trapped.

When a write to SVCR.ZA changes the value of PSTATE.ZA from 0 to 1, all implemented bits of the storage are set to zero.

Changes to this field do not have an effect on the SVE vector and predicate registers and FPSR.

A direct or indirect read of ZA appears to occur in program order relative to a direct write of SVCR, and to MSR SVCRZA and MSR SVCRSMZA instructions, without the need for explicit synchronization.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

SM, bit [0]

Enables Streaming SVE mode.

When the PE is in Streaming SVE mode, the Streaming SVE vector length (SVL) applies to SVE instructions, and execution at any Exception level of an instruction which is illegal in that mode is trapped. The exception is reported using an ESR_ELx.{EC, SMTC} value of {0x1D, 0x1}.

When the PE is not in Streaming SVE mode, the SVE vector length (VL) applies to SVE instructions, and execution at any Exception level of an instruction which is only legal in that mode is trapped. The exception is reported using an ESR_ELx.{EC, SMTC} value of {0x1D, 0x2}.

The possible values of this bit are:

SM	Meaning
0b0	The PE is not in Streaming SVE mode.
0b1	The PE is in Streaming SVE mode.

When a write to SVCR.SM changes the value of PSTATE.SM, the following applies:

When changed from 0 to 1, an entry to Streaming SVE mode is performed.
When changed from 1 to 0, an exit from Streaming SVE mode is performed.
All implemented bits of the SVE registers Z0-Z31, P0-P15, and FFR in the new mode are set to zero.
All bits in FPMR are set to zero.
FPSR in the new mode is set to 0x0000_0000_0800_009f, in which all cumulative status bits are set to 1.

Changes to this field do not have an effect on SME ZA storage or, if implemented, ZT0 storage.

A direct or indirect read of SM appears to occur in program order relative to a direct write of SVCR, and to MSR SVCRSM and MSR SVCRSMZA instructions, without the need for explicit synchronization.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Accessing SVCR

SVCR is read/write and can be accessed from any Exception level.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SVCR

op0	op1	CRn	CRm	op2
0b11	0b011	0b0100	0b0010	0b010

if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.ESM == '0' then UNDEFINED; elsif !ELIsInHost(EL0) && CPACR_EL1.SMEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); else AArch64.SystemAccessTrap(EL1, 0x1D); elsif ELIsInHost(EL0) && CPTR_EL2.SMEN != '11' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif ELIsInHost(EL2) && CPTR_EL2.SMEN IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else X[t, 64] = SVCR; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.ESM == '0' then UNDEFINED; elsif CPACR_EL1.SMEN IN {'x0'} then AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif ELIsInHost(EL2) && CPTR_EL2.SMEN IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else X[t, 64] = SVCR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.ESM == '0' then UNDEFINED; elsif !ELIsInHost(EL2) && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif ELIsInHost(EL2) && CPTR_EL2.SMEN IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else X[t, 64] = SVCR; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else X[t, 64] = SVCR;

MSR SVCR, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b011	0b0100	0b0010	0b010

if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.ESM == '0' then UNDEFINED; elsif !ELIsInHost(EL0) && CPACR_EL1.SMEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); else AArch64.SystemAccessTrap(EL1, 0x1D); elsif ELIsInHost(EL0) && CPTR_EL2.SMEN != '11' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif ELIsInHost(EL2) && CPTR_EL2.SMEN IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else SVCR = X[t, 64]; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.ESM == '0' then UNDEFINED; elsif CPACR_EL1.SMEN IN {'x0'} then AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif ELIsInHost(EL2) && CPTR_EL2.SMEN IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else SVCR = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.ESM == '0' then UNDEFINED; elsif !ELIsInHost(EL2) && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif ELIsInHost(EL2) && CPTR_EL2.SMEN IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else SVCR = X[t, 64]; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else SVCR = X[t, 64];

MSR SVCRSM, #<imm>

op0	op1	CRn	CRm	op2
0b00	0b011	0b0100	0b001x	0b011

MSR SVCRZA, #<imm>

op0	op1	CRn	CRm	op2
0b00	0b011	0b0100	0b010x	0b011

MSR SVCRSMZA, #<imm>

op0	op1	CRn	CRm	op2
0b00	0b011	0b0100	0b011x	0b011

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																														ZA	SM

SVCR, Streaming Vector Control Register

Purpose

Configuration