UAO

This register is present only when FEAT_UAO is implemented. Otherwise, direct accesses to UAO are UNDEFINED.

Attributes

Field descriptions

Bits [63:24]

UAO, bit [23]

User Access Override.

UAO	Meaning
0b0	The behavior of LDTR* and STTR* instructions is as defined in the base Armv8 architecture.
0b1	When executed at the following Exception levels, LDTR* and STTR* instructions behave as the equivalent LDR* and STR* instructions: EL1. EL2 when the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}.

UAO

Meaning

0b0

The behavior of LDTR* and STTR* instructions is as defined in the base Armv8 architecture.

0b1

When executed at the following Exception levels, LDTR* and STTR* instructions behave as the equivalent LDR* and STR* instructions:

EL1.
EL2 when the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}.

When executed at EL3, or at EL2 when the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, the LDTR* and STTR* instructions behave as the equivalent LDR* and STR* instructions, regardless of the setting of the PSTATE.UAO bit.

Bits [22:0]

Accessing UAO

For more information about the operation of the MSR (immediate) accessor, see 'MSR (immediate)'.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, UAO

op0	op1	CRn	CRm	op2
0b11	0b000	0b0100	0b0010	0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = Zeros(40):PSTATE.UAO:Zeros(23); elsif PSTATE.EL == EL2 then X[t, 64] = Zeros(40):PSTATE.UAO:Zeros(23); elsif PSTATE.EL == EL3 then X[t, 64] = Zeros(40):PSTATE.UAO:Zeros(23);

MSR UAO, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0100	0b0010	0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PSTATE.UAO = X[t, 64]<23>; elsif PSTATE.EL == EL2 then PSTATE.UAO = X[t, 64]<23>; elsif PSTATE.EL == EL3 then PSTATE.UAO = X[t, 64]<23>;

MSR UAO, #<imm>

op0	op1	CRn	op2
0b00	0b000	0b0100	0b011

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0								UAO	RES0

UAO, User Access Override

Purpose

Configuration