AMCR

Global control register for the activity monitors implementation. AMCR is applicable to both the architected and the auxiliary counter groups.

Configuration

External register AMCR bits [31:0] are architecturally mapped to AArch64 System register AMCR_EL0[31:0] when FEAT_AMU_EXT32 is implemented.

External register AMCR bits [63:0] are architecturally mapped to AArch64 System register AMCR_EL0[63:0] when FEAT_AMU_EXT64 is implemented.

External register AMCR bits [31:0] are architecturally mapped to AArch32 System register AMCR[31:0].

It is IMPLEMENTATION DEFINED whether AMCR is implemented in the Core power domain or in the Debug power domain.

This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCR are RES0.

Attributes

Field descriptions

When FEAT_AMU_EXT64 is implemented:

Bits [63:11]

HDBG, bit [10]

This bit controls whether activity monitor counting is halted when the PE is halted in Debug state.

HDBG	Meaning
0b0	Activity monitors do not halt counting when the PE is halted in Debug state.
0b1	Activity monitors halt counting when the PE is halted in Debug state.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [9:0]

Otherwise:

Bits [31:11]

HDBG, bit [10]

This bit controls whether activity monitor counting is halted when the PE is halted in Debug state.

HDBG	Meaning
0b0	Activity monitors do not halt counting when the PE is halted in Debug state.
0b1	Activity monitors halt counting when the PE is halted in Debug state.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [9:0]

Accessing AMCR

Accesses to this register use the following encodings:

When FEAT_AMU_EXT32 is implemented

Accessible at offset 0xE04 from AMU

Accesses on this interface are RO.

When FEAT_AMU_EXT64 is implemented

Accessible at offset 0xE10 from AMU

Accesses on this interface are RO.

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																					HDBG	RES0

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																					HDBG	RES0

AMCR, Activity Monitors Control Register

Purpose

Configuration

Attributes

Field descriptions

When FEAT_AMU_EXT64 is implemented:

Bits [63:11]

HDBG, bit [10]

Bits [9:0]

Otherwise:

Bits [31:11]

HDBG, bit [10]

Bits [9:0]

Accessing AMCR

When FEAT_AMU_EXT32 is implemented

When FEAT_AMU_EXT64 is implemented