CNTCR

Enables the counter, controls the counter frequency setting, and controls counter behavior during debug.

Configuration

It is IMPLEMENTATION DEFINED whether CNTCR is implemented in the Core power domain or in the Debug power domain.

For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.

Attributes

Field descriptions

Bits [31:18]

FCREQ, bits [17:8]

Frequency change request. Indicates the number of the entry in the Frequency modes table to select.

Selecting an unimplemented entry, or an entry that contains 0, has no effect on the counter.

The maximum number of entries in the Frequency modes table is IMPLEMENTATION DEFINED up to a maximum of 1004 entries, see 'The Frequency modes table'. An implementation is only required to implement an FCREQ field that can hold values from 0 to the highest supported Frequency modes table entry. Any unrequired most-significant bits of FCREQ can be implemented as RES0.

The reset behavior of this field is:

On a Timer reset, this field resets to 0.

Bits [7:3]

SCEN, bit [2]
When FEAT_CNTSC is implemented:

Scale Enable.

SCEN	Meaning
0b0	Scaling is not enabled. The counter value is incremented by 0x1.0000000 for each counter tick.
0b1	Scaling is enabled. The counter is incremented by CNTSCR.ScaleVal for each counter tick.

The SCEN bit can only be changed when the counter is disabled, when CNTCR.EN == 0.

If the value of CNTCR.SCEN changes when CNTCR.EN == 1 then:

The counter value becomes UNKNOWN.
The counter value remains UNKNOWN on future ticks of the clock.

When the CNTCV register in the CNTControlBase frame of the memory mapped counter module is written to, the accumulated fraction information is reset to zero.

The reset behavior of this field is:

On a Timer reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

HDBG, bit [1]

Halt-on-debug. Controls whether a Halt-on-debug signal halts the system counter:

HDBG	Meaning
0b0	System counter ignores Halt-on-debug.
0b1	Asserted Halt-on-debug signal halts system counter update.

The reset behavior of this field is:

On a Timer reset, this field resets to an architecturally UNKNOWN value.

EN, bit [0]

Enables the counter:

EN	Meaning
0b0	System counter disabled.
0b1	System counter enabled.

The reset behavior of this field is:

On a Timer reset, this field resets to 0.

Accessing CNTCR

In a system that supports the Realm Management Extension, the CNTControlBase frame, which includes this register, is implemented only in the Root physical address space.

In a system that supports Secure and Non-secure physical address spaces, the CNTControlBase frame, which includes this register, is implemented only in the Secure physical address space.

CNTCR can be accessed through the memory-mapped interfaces:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0														FCREQ										RES0					SCEN	HDBG	EN

CNTCR, Counter Control Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:18]

FCREQ, bits [17:8]

Bits [7:3]

SCEN, bit [2]
When FEAT_CNTSC is implemented:

Otherwise:

HDBG, bit [1]

EN, bit [0]

Accessing CNTCR

CNTCR can be accessed through the memory-mapped interfaces:

CNTCR, Counter Control Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:18]

FCREQ, bits [17:8]

Bits [7:3]

SCEN, bit [2]When FEAT_CNTSC is implemented:

Otherwise:

HDBG, bit [1]

EN, bit [0]

Accessing CNTCR

CNTCR can be accessed through the memory-mapped interfaces:

SCEN, bit [2]
When FEAT_CNTSC is implemented: