DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 - 63

The DBGBVR<n>_EL1 characteristics are:

Purpose

Holds a virtual address, or a VMID and/or a context ID, for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR<n>_EL1.

Configuration

External register DBGBVR<n>_EL1 bits [63:0] are architecturally mapped to AArch64 System register DBGBVR<n>_EL1[63:0].

External register DBGBVR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGBVR<n>[31:0].

External register DBGBVR<n>_EL1 bits [63:32] are architecturally mapped to AArch32 System register DBGBXVR<n>[31:0].

DBGBVR<n>_EL1 is in the Core power domain.

How this register is interpreted depends on the value of DBGBCR<n>_EL1.BT.

When DBGBCR<n>_EL1.BT is 0b0x0x, this register holds a virtual address.
When DBGBCR<n>_EL1.BT is 0b001x, 0b011x, or 0b110x, this register holds a Context ID.
When DBGBCR<n>_EL1.BT is 0b100x, this register holds a VMID.
When DBGBCR<n>_EL1.BT is 0b101x, this register holds a VMID and a Context ID.
When DBGBCR<n>_EL1.BT is 0b111x, this register holds two Context ID values.

For other values of DBGBCR<n>_EL1.BT, this register is RES0.

If breakpoint n is not implemented then accesses to this register are:

RES0 when IsCorePowered() && !DoubleLockStatus() && !OSLockStatus() && AllowExternalDebugAccess().
A CONSTRAINED UNPREDICTABLE choice of RES0 or ERROR otherwise.

Attributes

DBGBVR<n>_EL1 is a 64-bit register.

Field descriptions

When DBGBCR<n>_EL1.BT IN {0b0x0x}:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESS[14:8]							Bits[56:53]				Bits[52:49]				VA[48:2]
VA[48:2]																														RES0

RESS[14:8], bits [63:57]

Reserved, Sign extended. Software must treat this field as RES0 if the most significant bit of VA is 0 or RES0, and as RES1 if the most significant bit of VA is 1.

Hardware always ignores the value of these bits and it is IMPLEMENTATION DEFINED whether:

The bits are hardwired to a copy of the most significant bit of VA, meaning writes to these bits are ignored, and reads to the bits always return the hardwired value.
The value in those bits can be written, and reads will return the last value written. The value held in those bits is ignored by hardware.

Bits[56:53]
When FEAT_LVA3 is implemented:

VA[56:53], bits [3:0] of bits [56:53]

Extension to VA[48:2]. For more information, see VA[48:2].

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

RESS[7:4], bits [3:0] of bits [56:53]

Extension to RESS[14:8]. For more information, see RESS[14:8].

Bits[52:49]
When FEAT_LVA is implemented:

VA[52:49], bits [3:0] of bits [52:49]

Extension to VA[48:2]. For more information, see VA[48:2].

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

RESS[3:0], bits [3:0] of bits [52:49]

Extension to RESS[14:8]. For more information, see RESS[14:8].

VA[48:2], bits [48:2]

If the address is being matched in an AArch64 stage 1 translation regime:

This field contains bits[48:2] of the address for comparison.
When FEAT_LVA3 is implemented, (VA[56:53]:VA[52:49]) forms the upper part of the address value. If FEAT_LVA3 is not implemented, bits VA[56:53] are part of the RESS field.
When FEAT_LVA is implemented, VA[52:49] forms the upper part of the address value. If FEAT_LVA is not implemented, bits [52:49] are part of the RESS field.

If the address is being matched in an AArch32 stage 1 translation regime, the first 20 bits of this field are RES0, and the rest of the field contains bits[31:2] of the address for comparison.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [1:0]

Reserved, RES0.

When DBGBCR<n>_EL1.BT IN {0b001x}:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
ContextID

Bits [63:32]

Reserved, RES0.

ContextID, bits [31:0]

Context ID value for comparison.

The value is compared against CONTEXTIDR_EL2 when the Effective value of HCR_EL2.E2H is 1, and either:

The PE is executing at EL2.
HCR_EL2.TGE is 1, the PE is executing at EL0, and EL2 is enabled in the current Security state.

Otherwise, the value is compared against the following:

CONTEXTIDR when the PE is executing at AArch32.
CONTEXTIDR_EL1 when the PE is executing at AArch64.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

When DBGBCR<n>_EL1.BT IN {0b011x}, EL2 is implemented and (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented):

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
ContextID

Bits [63:32]

Reserved, RES0.

ContextID, bits [31:0]

Context ID value for comparison against CONTEXTIDR_EL1.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

When DBGBCR<n>_EL1.BT IN {0b100x} and EL2 is implemented:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																VMID[15:8]								VMID[7:0]
RES0

Bits [63:48]

Reserved, RES0.

VMID[15:8], bits [47:40]
When FEAT_VHE is implemented and VTCR_EL2.VS == 1:

Extension to VMID[7:0]. For more information, see DBGBVR<n>_EL1.VMID[7:0].

If EL2 is using AArch32, this field is RES0.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Reserved, RES0.

VMID[7:0], bits [39:32]

VMID value for comparison.

The VMID is 8 bits when any of the following are true:

EL2 is using AArch32.
VTCR_EL2.VS is 0.
FEAT_VMID16 is not implemented.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [31:0]

Reserved, RES0.

When DBGBCR<n>_EL1.BT IN {0b101x} and EL2 is implemented:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																VMID[15:8]								VMID[7:0]
ContextID

Bits [63:48]

Reserved, RES0.

VMID[15:8], bits [47:40]
When FEAT_VMID16 is implemented and VTCR_EL2.VS == 1:

Extension to VMID[7:0]. For more information, see DBGBVR<n>_EL1.VMID[7:0].

If EL2 is using AArch32, or if the implementation has an 8-bit VMID, this field is RES0.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Reserved, RES0.

VMID[7:0], bits [39:32]

VMID value for comparison.

The VMID is 8 bits when any of the following are true:

EL2 is using AArch32.
VTCR_EL2.VS is 0.
FEAT_VMID16 is not implemented.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

ContextID, bits [31:0]

Context ID value for comparison against CONTEXTIDR_EL1.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

When DBGBCR<n>_EL1.BT IN {0b110x}, EL2 is implemented and (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented):

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ContextID2
RES0

ContextID2, bits [63:32]

Context ID value for comparison against CONTEXTIDR_EL2.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [31:0]

Reserved, RES0.

When DBGBCR<n>_EL1.BT IN {0b111x}, EL2 is implemented and (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented):

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ContextID2
ContextID

ContextID2, bits [63:32]

Context ID value for comparison against CONTEXTIDR_EL2.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

ContextID, bits [31:0]

Context ID value for comparison against CONTEXTIDR_EL1.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing DBGBVR<n>_EL1

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalDebugAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

DBGBVR<n>_EL1 can be accessed through the external debug interface:

Component	Offset	Instance	Range
Debug	0x400 + (16 * n)	DBGBVR<n>_EL1	63:0

This interface is accessible as follows:

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalDebugAccess(), accesses to this register generate an error response.
When SoftwareLockStatus(), accesses to this register are RO.
Otherwise, accesses to this register are RW.

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 - 63

Purpose

Configuration

Attributes

Field descriptions

When DBGBCR<n>_EL1.BT IN {0b0x0x}:

RESS[14:8], bits [63:57]

Bits[56:53]When FEAT_LVA3 is implemented:

VA[56:53], bits [3:0] of bits [56:53]

Otherwise:

RESS[7:4], bits [3:0] of bits [56:53]

Bits[52:49]When FEAT_LVA is implemented:

VA[52:49], bits [3:0] of bits [52:49]

Otherwise:

RESS[3:0], bits [3:0] of bits [52:49]

VA[48:2], bits [48:2]

Bits [1:0]

When DBGBCR<n>_EL1.BT IN {0b001x}:

Bits [63:32]

ContextID, bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b011x}, EL2 is implemented and (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented):

Bits [63:32]

ContextID, bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b100x} and EL2 is implemented:

Bits [63:48]

VMID[15:8], bits [47:40]When FEAT_VHE is implemented and VTCR_EL2.VS == 1:

Otherwise:

VMID[7:0], bits [39:32]

Bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b101x} and EL2 is implemented:

Bits [63:48]

VMID[15:8], bits [47:40]When FEAT_VMID16 is implemented and VTCR_EL2.VS == 1:

Otherwise:

VMID[7:0], bits [39:32]

ContextID, bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b110x}, EL2 is implemented and (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented):

ContextID2, bits [63:32]

Bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b111x}, EL2 is implemented and (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented):

ContextID2, bits [63:32]

ContextID, bits [31:0]

Accessing DBGBVR<n>_EL1

DBGBVR<n>_EL1 can be accessed through the external debug interface:

Bits[56:53]
When FEAT_LVA3 is implemented:

Bits[52:49]
When FEAT_LVA is implemented:

VMID[15:8], bits [47:40]
When FEAT_VHE is implemented and VTCR_EL2.VS == 1:

VMID[15:8], bits [47:40]
When FEAT_VMID16 is implemented and VTCR_EL2.VS == 1: