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Proprietary Notice

EDECCR, External Debug Exception Catch Control Register

The EDECCR characteristics are:

Purpose

Controls Exception Catch debug events. For more information, see 'Exception Catch debug event'.

Configuration

External register EDECCR bits [31:0] are architecturally mapped to AArch64 System register OSECCR_EL1[31:0].

External register EDECCR bits [31:0] are architecturally mapped to AArch32 System register DBGOSECCR[31:0].

EDECCR is in the Core power domain.

Attributes

EDECCR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0RLR2RLR1RLR0RES0RLE2RLE1RLE0NSR3NSR2NSR1NSR0SR3SR2SR1SR0NSE3NSE2NSE1NSE0SE3SE2SE1SE0

Bits [31:23]

Reserved, RES0.

RLR2, bit [22]
When FEAT_RME is implemented:

Controls exception catch on exception return to Realm EL2 in conjunction with EDECCR.RLE2.

RLR2Meaning
0b0

If EDECCR.RLE2 is 0, then Exception Catch debug events are disabled for Realm EL2.

If EDECCR.RLE2 is 1, then Exception Catch debug events are enabled for exception entry and exception return to Realm EL2.

0b1

If EDECCR.RLE2 is 0, then Exception Catch debug events are enabled for exception returns to Realm EL2.

If EDECCR.RLE2 is 1, then Exception Catch debug events are enabled for exception entry to Realm EL2.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

RLR1, bit [21]
When FEAT_RME is implemented:

Controls exception catch on exception return to Realm EL1 in conjunction with EDECCR.RLE1.

RLR1Meaning
0b0

If EDECCR.RLE1 is 0, then Exception Catch debug events are disabled for Realm EL1.

If EDECCR.RLE1 is 1, then Exception Catch debug events are enabled for exception entry and exception return to Realm EL1.

0b1

If EDECCR.RLE1 is 0, then Exception Catch debug events are enabled for exception returns to Realm EL1.

If EDECCR.RLE1 is 1, then Exception Catch debug events are enabled for exception entry to Realm EL1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

RLR0, bit [20]
When FEAT_RME is implemented:

Controls exception catch on exception return to Realm EL0.

RLR0Meaning
0b0

Exception Catch debug events are disabled for Realm EL0.

0b1

Exception Catch debug events are enabled for exception returns to Realm EL0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [19]

Reserved, RES0.

RLE2, bit [18]
When FEAT_RME is implemented:

Controls exception catch on exception entry to Realm EL2. Also controls exception catch on exception return to Realm EL2 in conjunction with EDECCR.RLR2.

RLE2Meaning
0b0

If EDECCR.RLR2 is 0, then Exception Catch debug events are disabled for Realm EL2.

If EDECCR.RLR2 is 1, then Exception Catch debug events are enabled for exception returns to Realm EL2.

0b1

If EDECCR.RLR2 is 0, then Exception Catch debug events are enabled for exception entry and exception return to Realm EL2.

If EDECCR.RLR2 is 1, then Exception Catch debug events are enabled for exception entry to Realm EL2.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

RLE1, bit [17]
When FEAT_RME is implemented:

Controls exception catch on exception entry to Realm EL1. Also controls exception catch on exception return to Realm EL1 in conjunction with EDECCR.RLR1.

RLE1Meaning
0b0

If EDECCR.RLR1 is 0, then Exception Catch debug events are disabled for Realm EL1.

If EDECCR.RLR1 is 1, then Exception Catch debug events are enabled for exception returns to Realm EL1.

0b1

If EDECCR.RLR1 is 0, then Exception Catch debug events are enabled for exception entry and exception return to Realm EL1.

If EDECCR.RLR1 is 1, then Exception Catch debug events are enabled for exception entry to Realm EL1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

RLE0, bit [16]

Access to this field is RES0 .

NSR3, bit [15]

Access to this field is RES0 .

NSR2, bit [14]
When FEAT_Debugv8p2 is implemented and Non-secure EL2 is implemented:

Controls exception catch on exception return to Non-secure EL2 in conjunction with EDECCR.NSE2.

NSR2Meaning
0b0

If EDECCR.NSE2 is 0, then Exception Catch debug events are disabled for Non-secure EL2.

If EDECCR.NSE2 is 1, then Exception Catch debug events are enabled for exception entry, reset entry, and exception return to Non-secure EL2.

0b1

If EDECCR.NSE2 is 0, then Exception Catch debug events are enabled for exception returns to Non-secure EL2.

If EDECCR.NSE2 is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Non-secure EL2.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSR1, bit [13]
When FEAT_Debugv8p2 is implemented and Non-secure EL1 is implemented:

Controls exception catch on exception return to Non-secure EL1 in conjunction with EDECCR.NSE1.

NSR1Meaning
0b0

If EDECCR.NSE1 is 0, then Exception Catch debug events are disabled for Non-secure EL1.

If EDECCR.NSE1 is 1, then Exception Catch debug events are enabled for exception entry, reset entry, and exception return to Non-secure EL1.

0b1

If EDECCR.NSE1 is 0, then Exception Catch debug events are enabled for exception returns to Non-secure EL1.

If EDECCR.NSE1 is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Non-secure EL1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSR0, bit [12]
When FEAT_Debugv8p2 is implemented and Non-secure EL0 is implemented:

Controls exception catch on exception return to Non-secure EL0.

NSR0Meaning
0b0

Exception Catch debug events are disabled for Non-secure EL0.

0b1

Exception Catch debug events are enabled for exception returns to Non-secure EL0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SR3, bit [11]
When FEAT_Debugv8p2 is implemented and EL3 is implemented:

Controls exception catch on exception return to EL3 in conjunction with EDECCR.SE3.

SR3Meaning
0b0

If EDECCR.SE3 is 0, then Exception Catch debug events are disabled for EL3.

If EDECCR.SE3 is 1, then Exception Catch debug events are enabled for exception entry, reset entry, and exception return to EL3.

0b1

If EDECCR.SE3 is 0, then Exception Catch debug events are enabled for exception returns to EL3.

If EDECCR.SE3 is 1, then Exception Catch debug events are enabled for exception entry and reset entry to EL3.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SR2, bit [10]
When FEAT_Debugv8p2 is implemented and FEAT_SEL2 is implemented:

Controls exception catch on exception return to Secure EL2 in conjunction with EDECCR.SE2.

SR2Meaning
0b0

If EDECCR.SE2 is 0, then Exception Catch debug events are disabled for Secure EL2.

If EDECCR.SE2 is 1, then Exception Catch debug events are enabled for exception entry, reset entry, and exception return to Secure EL2.

0b1

If EDECCR.SE2 is 0, then Exception Catch debug events are enabled for exception returns to Secure EL2.

If EDECCR.SE2 is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Secure EL2.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SR1, bit [9]
When FEAT_Debugv8p2 is implemented and Secure EL1 is implemented:

Controls exception catch on exception return to Secure EL1 in conjunction with EDECCR.SE1.

SR1Meaning
0b0

If EDECCR.SE1 is 0, then Exception Catch debug events are disabled for Secure EL1.

If EDECCR.SE1 is 1, then Exception Catch debug events are enabled for exception entry, reset entry, and exception return to Secure EL1.

0b1

If EDECCR.SE1 is 0, then Exception Catch debug events are enabled for exception returns to Secure EL1.

If EDECCR.SE1 is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Secure EL1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SR0, bit [8]
When FEAT_Debugv8p2 is implemented and Secure EL0 is implemented:

Controls exception catch on exception return to Secure EL0.

SR0Meaning
0b0

Exception Catch debug events are disabled for Secure EL0.

0b1

Exception Catch debug events are enabled for exception returns to Secure EL0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSE3, bit [7]

Access to this field is RES0 .

NSE2, bit [6]
When FEAT_Debugv8p2 is implemented and Non-secure EL2 is implemented:

Controls exception catch on exception entry to Non-secure EL2. Also controls exception catch on exception return to Non-secure EL2 in conjunction with EDECCR.NSR2.

NSE2Meaning
0b0

If EDECCR.NSR2 is 0, then Exception Catch debug events are disabled for Non-secure EL2.

If EDECCR.NSR2 is 1, then Exception Catch debug events are enabled for exception returns to Non-secure EL2.

0b1

If EDECCR.NSR2 is 0, then Exception Catch debug events are enabled for exception entry, reset entry, and exception return to Non-secure EL2.

If EDECCR.NSR2 is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Non-secure EL2.

Note

It is IMPLEMENTATION DEFINED whether a reset entry to an Exception level will generate an Exception Catch debug event.

The reset behavior of this field is:


When Non-secure EL2 is implemented:

Coarse-grained exception catch for Non-secure EL2. Controls Exception Catch debug events for Non-secure EL2.

NSE2Meaning
0b0

Exception Catch debug events are disabled for Non-secure EL2.

0b1

Exception Catch debug events are enabled for Non-secure EL2.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSE1, bit [5]
When FEAT_Debugv8p2 is implemented and Non-secure EL1 is implemented:

Controls exception catch on exception entry to Non-secure EL1. Also controls exception catch on exception return to Non-secure EL1 in conjunction with EDECCR.NSR1.

NSE1Meaning
0b0

If EDECCR.NSR1 is 0, then Exception Catch debug events are disabled for Non-secure EL1.

If EDECCR.NSR1 is 1, then Exception Catch debug events are enabled for exception returns to Non-secure EL1.

0b1

If EDECCR.NSR1 is 0, then Exception Catch debug events are enabled for exception entry, reset entry, and exception return to Non-secure EL1.

If EDECCR.NSR1 is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Non-secure EL1.

Note

It is IMPLEMENTATION DEFINED whether a reset entry to an Exception level will generate an Exception Catch debug event.

The reset behavior of this field is:


When Non-secure EL1 is implemented:

Coarse-grained exception catch for Non-secure EL1. Controls Exception Catch debug events for Non-secure EL1.

NSE1Meaning
0b0

Exception Catch debug events are disabled for Non-secure EL1.

0b1

Exception Catch debug events are enabled for Non-secure EL1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSE0, bit [4]

Access to this field is RES0 .

SE3, bit [3]
When FEAT_Debugv8p2 is implemented and EL3 is implemented:

Controls exception catch on exception entry to EL3. Also controls exception catch on exception return to EL3 in conjunction with EDECCR.SR3.

SE3Meaning
0b0

If EDECCR.SR3 is 0, then Exception Catch debug events are disabled for EL3.

If EDECCR.SR3 is 1, then Exception Catch debug events are enabled for exception returns to EL3.

0b1

If EDECCR.SR3 is 0, then Exception Catch debug events are enabled for exception entry, reset entry, and exception return to EL3.

If EDECCR.SR3 is 1, then Exception Catch debug events are enabled for exception entry and reset entry to EL3.

Note

It is IMPLEMENTATION DEFINED whether a reset entry to an Exception level will generate an Exception Catch debug event.

The reset behavior of this field is:


When FEAT_Debugv8p2 is not implemented and EL3 is implemented:

Coarse-grained exception catch for EL3. Controls Exception Catch debug events for EL3.

SE3Meaning
0b0

Exception Catch debug events are disabled for EL3.

0b1

Exception Catch debug events are enabled for EL3.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SE2, bit [2]
When FEAT_Debugv8p2 is implemented and FEAT_SEL2 is implemented:

Controls exception catch on exception entry to Secure EL2. Also controls exception catch on exception return to Secure EL2 in conjunction with EDECCR.SR2.

SE2Meaning
0b0

If EDECCR.SR2 is 0, then Exception Catch debug events are disabled for Secure EL2.

If EDECCR.SR2 is 1, then Exception Catch debug events are enabled for exception returns to Secure EL2.

0b1

If EDECCR.SR2 is 0, then Exception Catch debug events are enabled for exception entry, reset entry, and exception return to Secure EL2.

If EDECCR.SR2 is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Secure EL2.

Note

It is IMPLEMENTATION DEFINED whether a reset entry to an Exception level will generate an Exception Catch debug event.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SE1, bit [1]
When FEAT_Debugv8p2 is implemented and Secure EL1 is implemented:

Controls exception catch on exception entry to Secure EL1. Also controls exception catch on exception return to Secure EL1 in conjunction with EDECCR.SR1.

SE1Meaning
0b0

If EDECCR.SR1 is 0, then Exception Catch debug events are disabled for Secure EL1.

If EDECCR.SR1 is 1, then Exception Catch debug events are enabled for exception returns to Secure EL1.

0b1

If EDECCR.SR1 is 0, then Exception Catch debug events are enabled for exception entry, reset entry, and exception return to Secure EL1.

If EDECCR.SR1 is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Secure EL1.

Note

It is IMPLEMENTATION DEFINED whether a reset entry to an Exception level will generate an Exception Catch debug event.

The reset behavior of this field is:


When Secure EL1 is implemented:

Coarse-grained exception catch for Secure EL1. Controls Exception Catch debug events for Secure EL1.

SE1Meaning
0b0

Exception Catch debug events are disabled for Secure EL1.

0b1

Exception Catch debug events are enabled for Secure EL1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SE0, bit [0]

Access to this field is RES0 .

Accessing EDECCR

EDECCR can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0x098EDECCR

This interface is accessible as follows:

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
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Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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