EDPRSR, External Debug Processor Status Register

Reserved, RES0.

External Performance Monitors Access Disable Extended Status. Together with EDPRSR.EPMAD, reports whether access to Performance Monitor registers by an external debugger is permitted.

For a description of the values derived by evaluating EPMAD and EPMADE together, see EDPRSR.EPMAD.

Reserved, RES0.

External Trace Access Disable Extended Status. Together with EDPRSR.ETAD, reports whether access to trace unit registers by an external debugger is permitted.

For a description of the values derived by evaluating ETAD and ETADE together, see EDPRSR.ETAD.

Reserved, RES0.

External Debug Access Disable Extended Status. Together with EDPRSR.EDAD, reports whether access to breakpoint registers, watchpoint registers, and OSLAR_EL1 by an external debugger is permitted.

For a description of the values derived by evaluating EDAD and EDADE together, see EDPRSR.EDAD.

Reserved, RES0.

Sticky ETAD error. Set to 1 when a Non-secure external debug interface access to an external trace register returns an error because AllowExternalTraceAccess() == FALSE for the access.

STAD	Meaning
0b0	Since EDPRSR was last read, no external accesses to the trace unit registers have failed because AllowExternalTraceAccess() was FALSE for the access.
0b1	Since EDPRSR was last read, at least one external access to the trace unit registers has failed because AllowExternalTraceAccess() was FALSE for the access.

If IsCorePowered() == TRUE, the Core power domain is powered up, then, following a read of EDPRSR:

• If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE then this bit clears to 0.
• If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE then it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This bit is in the Core power domain.

The reset behavior of this field is:

• On a Cold reset, this field resets to 0.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if DoubleLockStatus() or FEAT_DoPD is not implemented and !IsCorePowered() or EDPRSR.R == 1.
• Otherwise, access to this field is RC/WI.

Reserved, RES0.

External Trace Access Disable Status. Together with EDPRSR.ETADE, reports whether access to trace unit registers by an external debugger is permitted.

ETADE	ETAD	Meaning
0b0	0b0	Access to trace unit registers by an external debugger is permitted.
0b0	0b1	Root and Secure access to trace unit registers by an external debugger is permitted. Realm and Non-secure access to trace unit registers by an external debugger is not permitted.
0b1	0b0	Root and Realm access to trace unit registers by an external debugger is permitted. Secure and Non-secure access to trace unit registers by an external debugger is not permitted.
0b1	0b1	Root access to trace unit registers by an external debugger is permitted. Secure, Non-secure, and Realm access to trace unit registers by an external debugger is not permitted.

External Trace Access Disable status.

ETAD	Meaning
0b0	External Non-secure trace unit accesses enabled. AllowExternalTraceAccess() == TRUE for a Non-secure access.
0b1	External Non-secure trace unit accesses disabled. AllowExternalTraceAccess() == FALSE for a Non-secure access.

This bit is in the Core power domain.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if DoubleLockStatus() or FEAT_DoPD is not implemented and !IsCorePowered() or EDPRSR.R == 1.
• Otherwise, access to this field is RO.

Reserved, RES0.

Sticky Debug Restart. Set to 1 when the PE exits Debug state.

Permitted values are:

SDR	Meaning
0b0	The PE has not restarted since EDPRSR was last read.
0b1	The PE has restarted since EDPRSR was last read.

If the Core power domain is powered up, then following a read of EDPRSR:

• If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE this bit clears to 0.
• If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This field is in the Core power domain.

The reset behavior of this field is:

• On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or DoubleLockStatus() or EDPRSR.R == 1.
• When SoftwareLockStatus(), access to this field is RO.
• Otherwise, access to this field is RC/WI.

Sticky EPMAD error. Set to 1 if an external debug interface access to a Performance Monitors register returns an error because AllowExternalPMUAccess() == FALSE.

Permitted values are:

SPMAD	Meaning
0b0	No Non-secure external debug interface accesses to the external Performance Monitors registers have failed because AllowExternalPMUAccess() == FALSE for the access since EDPRSR was last read.
0b1	At least one Non-secure external debug interface access to the external Performance Monitors register has failed and returned an error because AllowExternalPMUAccess() == FALSE for the access since EDPRSR was last read.

If the Core power domain is powered up, then following a read of EDPRSR:

• If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, this bit clears to 0.
• If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This field is in the Core power domain.

The reset behavior of this field is:

• On a Cold reset, this field resets to 0.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or DoubleLockStatus() or EDPRSR.R == 1.
• When SoftwareLockStatus(), access to this field is RO.
• Otherwise, access to this field is RC/WI.

Sticky EPMAD error.

SPMAD	Meaning
0b0	No external debug interface accesses to the Performance Monitors registers have failed because AllowExternalPMUAccess() == FALSE since EDPRSR was last read.
0b1	At least one external debug interface access to the Performance Monitors registers has failed and returned an error because AllowExternalPMUAccess() == FALSE since EDPRSR was last read.

If the Core power domain is powered up, then, following a read of EDPRSR:

• If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, this bit clears to 0.
• If FEAT_DoubleLock is implemented, and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This field is in the Core power domain.

The reset behavior of this field is:

• On a Cold reset, this field resets to 0.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or OSLockStatus() or DoubleLockStatus() or EDPRSR.R == 1.
• When SoftwareLockStatus(), access to this field is RO.
• Otherwise, access to this field is RC/WI.

Reserved, RES0.

External Performance Monitors Access Disable Status. Together with EDPRSR.EPMADE, reports whether access to Performance Monitor registers by an external debugger is permitted.

EPMADE	EPMAD	Meaning
0b0	0b0	Access to Performance Monitor registers by an external debugger is permitted.
0b0	0b1	Root and Secure access to Performance Monitor registers by an external debugger is permitted. Realm and Non-secure access to Performance Monitor registers by an external debugger is not permitted.
0b1	0b0	Root and Realm access to Performance Monitor registers by an external debugger is permitted. Secure and Non-secure access to Performance Monitor registers by an external debugger is not permitted.
0b1	0b1	Root access to Performance Monitor registers by an external debugger is permitted. Secure, Non-secure, and Realm access to Performance Monitor registers by an external debugger is not permitted.

External Performance Monitors Non-secure Access Disable status.

EPMAD	Meaning
0b0	External Non-secure Performance Monitors access enabled. AllowExternalPMUAccess() == TRUE for a Non-secure access.
0b1	External Non-secure Performance Monitors access disabled. AllowExternalPMUAccess() == FALSE for a Non-secure access.

This field is in the Core power domain.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or DoubleLockStatus() or EDPRSR.R == 1.
• Otherwise, access to this field is RO.

External Performance Monitors access disable status.

EPMAD	Meaning
0b0	External Performance Monitors access enabled. AllowExternalPMUAccess() == TRUE.
0b1	External Performance Monitors access disabled. AllowExternalPMUAccess() == FALSE.

This field is in the Core power domain.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or OSLockStatus() or DoubleLockStatus() or EDPRSR.R == 1.
• Otherwise, access to this field is RO.

Reserved, UNKNOWN.

Reserved, RES0.

Sticky EDAD error. Set to 1 if an external debug interface access to a debug register returns an error because AllowExternalDebugAccess() == FALSE.

SDAD	Meaning
0b0	No Non-secure external debug interface accesses to the debug registers have failed because AllowExternalDebugAccess() == FALSE for the access since EDPRSR was last read.
0b1	At least one Non-secure external debug interface access to the debug registers has failed and returned an error because AllowExternalDebugAccess() == FALSE for the access since EDPRSR was last read.

If the Core power domain is powered up, then, following a read of EDPRSR:

• If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE this bit clears to 0.
• If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This field is in the Core power domain.

The reset behavior of this field is:

• On a Cold reset, this field resets to 0.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or DoubleLockStatus() or EDPRSR.R == 1.
• Otherwise, access to this field is RO.

Sticky EDAD error. Set to 1 if an external debug interface access to a debug register returns an error because AllowExternalDebugAccess() == FALSE.

SDAD	Meaning
0b0	No external debug interface accesses to the debug registers have failed because AllowExternalDebugAccess() == FALSE since EDPRSR was last read.
0b1	At least one external debug interface access to the debug registers has failed and returned an error because AllowExternalDebugAccess() == FALSE since EDPRSR was last read.

If the Core power domain is powered up, then, following a read of EDPRSR:

• If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE this bit clears to 0.
• If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This bit is UNKNOWN on reads if OSLockStatus() == TRUE and external debug writes to OSLAR_EL1 do not return an error when AllowExternalDebugAccess() == FALSE.

This field is in the Core power domain.

The reset behavior of this field is:

• On a Cold reset, this field resets to 0.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or DoubleLockStatus() or EDPRSR.R == 1.
• Otherwise, access to this field is RO.

External Debug Access Disable Status. Together with EDPRSR.EDADE, reports whether access to breakpoint registers, watchpoint registers, and OSLAR_EL1 by an external debugger is permitted.

EDADE	EDAD	Meaning
0b0	0b0	Access to Debug registers by an external debugger is permitted.
0b0	0b1	Root and Secure access to Debug registers by an external debugger is permitted. Realm and Non-secure access to Debug registers by an external debugger is not permitted.
0b1	0b0	Root and Realm access to Debug registers by an external debugger is permitted. Secure and Non-secure access to Debug registers by an external debugger is not permitted.
0b1	0b1	Root access to Debug registers by an external debugger is permitted. Secure, Non-secure, and Realm access to Debug registers by an external debugger is not permitted.

External Debug Access Disable status.

EDAD	Meaning
0b0	External Non-secure access to breakpoint registers, watchpoint registers, and OSLAR_EL1 enabled. AllowExternalDebugAccess() == TRUE for a Non-secure access.
0b1	External Non-secure access to breakpoint registers, watchpoint registers, and OSLAR_EL1 disabled. AllowExternalDebugAccess() == FALSE for a Non-secure access.

This field is in the Core power domain.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or DoubleLockStatus() or EDPRSR.R == 1.
• Otherwise, access to this field is RO.

External Debug Access Disable status.

EDAD	Meaning
0b0	External access to breakpoint registers, watchpoint registers, and OSLAR_EL1 enabled. AllowExternalDebugAccess() == TRUE.
0b1	External access to breakpoint registers, watchpoint registers, and OSLAR_EL1 disabled. AllowExternalDebugAccess() == FALSE.

This bit is not valid and reads UNKNOWN if OSLockStatus() == TRUE and external debug writes to OSLAR_EL1 do not return an error when AllowExternalDebugAccess() == FALSE.

This field is in the Core power domain.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or DoubleLockStatus() or EDPRSR.R == 1.
• Otherwise, access to this field is RO.

External Debug Access Disable status.

EDAD	Meaning
0b0	External access to breakpoint registers, watchpoint registers, and OSLAR_EL1 enabled. AllowExternalDebugAccess() == TRUE.
0b1	External access to breakpoint registers, watchpoint registers disabled. It is IMPLEMENTATION DEFINED whether accesses to OSLAR_EL1 are enabled or disabled. AllowExternalDebugAccess() == FALSE.

This field is in the Core power domain.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or DoubleLockStatus() or EDPRSR.R == 1.
• Otherwise, access to this field is RO.

This field is RES0.

Double Lock.

From Armv8.2, this field is deprecated.

This field is in the Core power domain.

Accessing this field has the following behavior:

• Access is RAZ/WI if IsCorePowered() and !DoubleLockStatus().
• Otherwise, access to this field is UNKNOWN/WI.

Double Lock.

This field returns the result of the pseudocode function DoubleLockStatus().

If the Core power domain is powered up and DoubleLockStatus() == TRUE, it is IMPLEMENTATION DEFINED whether:

• EDPRSR.PU reads as 1, EDPRSR.DLK reads as 1, and EDPRSR.SPD is UNKNOWN.
• EDPRSR.PU reads as 0, EDPRSR.DLK is UNKNOWN, and EDPRSR.SPD reads as 0.

This field is in the Core power domain.

DLK	Meaning
0b0	DoubleLockStatus() returns FALSE.
0b1	DoubleLockStatus() returns TRUE and the Core power domain is powered up.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered().
• Otherwise, access to this field is RO.

Reserved, RES0.

OS Lock status bit.

A read of this bit returns the value of OSLSR_EL1.OSLK.

This field is in the Core power domain.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() and DoubleLockStatus() and EDPRSR.R == 1.
• Otherwise, access to this field is RO.

Halted status bit.

HALTED	Meaning
0b0	PE is in Non-debug state.
0b1	PE is in Debug state.

This field is in the Core power domain.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered().
• Otherwise, access to this field is RO.

Sticky core Reset status bit.

Permitted values are:

SR	Meaning
0b0	The non-debug logic of the PE is not in reset state and has not been reset since the last time EDPRSR was read.
0b1	The non-debug logic of the PE is in reset state or has been reset since the last time EDPRSR was read.

If EDPRSR.PU reads as 1 and EDPRSR.R reads as 0, which means that the Core power domain is in a powerup state and that the non-debug logic of the PE is not in reset state, then following a read of EDPRSR:

• If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE this bit clears to 0.
• If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

This field is in the Core power domain.

The reset behavior of this field is:

• On a Warm reset, this field resets to 1.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or DoubleLockStatus().
• When SoftwareLockStatus(), access to this field is RO.
• Otherwise, access to this field is RC/WI.

PE Reset status bit.

Permitted values are:

R	Meaning
0b0	The non-debug logic of the PE is not in reset state.
0b1	The non-debug logic of the PE is in reset state.

If FEAT_DoubleLock is implemented, the PE is in reset state, and the PE entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information, see 'EDPRSR.{DLK, R} and reset state'.

This field is in the Core power domain.

Accessing this field has the following behavior:

• Access is UNKNOWN/WI if FEAT_DoPD is not implemented and !IsCorePowered() or DoubleLockStatus().
• Otherwise, access to this field is RO.

Sticky core Powerdown status bit.

If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, then:

• If FEAT_Debugv8p2 is implemented, this bit reads as 0.
• If FEAT_Debugv8p2 is not implemented, this bit might read as 0 or 1.

For more information, see 'EDPRSR.{DLK, SPD, PU} and the Core power domain'.

SPD	Meaning
0b0	If EDPRSR.PU is 0, it is not known whether the state of the debug registers in the Core power domain is lost. If EDPRSR.PU is 1, the state of the debug registers in the Core power domain has not been lost.
0b1	The state of the debug registers in the Core power domain has been lost.

If the Core power domain is powered up, then, following a read of EDPRSR:

• If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE this bit clears to 0.
• If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.

EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} and the Core power domain'.

When FEAT_DoPD is not implemented and the Core power domain is in either retention or powerdown state, the value of EDPRSR.SPD is IMPLEMENTATION DEFINED. For more information, see 'EDPRSR.SPD when the Core domain is in either retention or powerdown state'.

The reset behavior of this field is:

• On a Cold reset, this field resets to 1.

Accessing this field has the following behavior:

• Access is RAZ/WI if FEAT_DoPD is not implemented and !IsCorePowered().
• Access is UNKNOWN/WI if IsCorePowered() and DoubleLockStatus().
• Otherwise, access to this field is RO.

Core powerup status bit.

Access to this field is RAO/WI.

Core Powerup status bit. Indicates whether the debug registers in the Core power domain can be accessed.

PU	Meaning
0b0	Either the Core power domain is in a low-power or powerdown state, or FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, meaning the debug registers in the Core power domain cannot be accessed.
0b1	The Core power domain is in a powerup state, and either FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, meaning the debug registers in the Core power domain can be accessed.

If FEAT_DoubleLock is implemented, the PE is in reset state, and the PE entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information, see 'EDPRSR.{DLK, R} and reset state'

EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} and the Core power domain'

Access to this field is RO.

Core Powerup status bit. Indicates whether the debug registers in the Core power domain can be accessed.

PU	Meaning
0b0	Core power domain is in a low-power or powerdown state where the debug registers in the Core power domain cannot be accessed.
0b1	Core power domain is in a powerup state where the debug registers in the Core power domain can be accessed.

If FEAT_DoubleLock is implemented, the PE is in reset state, and the PE entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information see 'EDPRSR.{DLK, R} and reset state'

EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} and the Core power domain'.

When the Core power domain is powered-up and DoubleLockStatus() == TRUE, then the value of EDPRSR.PU is IMPLEMENTATION DEFINED. See the description of the DLK bit for more information.

If FEAT_DoubleLock is implemented, the Core power domain is powered up, and DoubleLockStatus() == TRUE, it is IMPLEMENTATION DEFINED whether this bit reads as 0 or 1.

Access to this field is RO.