ERRACR

This register is present only when (Root state is implemented or Secure state is implemented) and an implementation implements ERRACR. Otherwise, direct accesses to ERRACR are RES0.

Attributes

Field descriptions

IMPLEMENTATION DEFINED, bits [63:32]

IMPLEMENTATION DEFINED observation controls. Additional IMPLEMENTATION DEFINED access control bits.

Bit [31]

Reserved, RAO.

Indicates ERRACR is present.

This field reads-as-one.

Bits [30:6]

RLRA, bits [5:4]
When FEAT_RME is implemented and the error record group allows configuration of Secure and Realm register accesses:

Realm Restricted Access. Controls Realm access to error records and interrupt configuration registers in the error record group.

RLRA	Meaning
0b00	Realm access is disabled. All error record, ERR<irq>CR<m>, and ERRIRQSR registers are RAZ/WI to Realm accesses.
0b01	Realm read access is enabled. Realm writes are ignored.
0b11	Realm read/write access is allowed. If the error record group supports MSIs, generated MSIs are always Non-secure.

All other values are reserved.

This control applies to all error record registers (ERR<n>*, including fault injection registers ERR<n>PFG* if implemented), and interrupt configuration registers (ERR<irq>CR<m> and ERRIRQSR, if implemented) in the error record group. The effect on any IMPLEMENTATION DEFINED registers is IMPLEMENTATION DEFINED.

When Realm access to error records is disabled, a Realm read of ERRGSR will return the error record status for the error records that cannot be accessed.

When Realm access is fully or partially disabled, the effect on Realm accesses to IMPLEMENTATION DEFINED registers is IMPLEMENTATION DEFINED.

Note

Realm access to error records is enabled from reset.

The reset behavior of this field is:

On an Error recovery reset, this field resets to 3.

Otherwise:

SRA, bits [3:2]
When Secure state is implemented, FEAT_RME is implemented and the error record group allows configuration of Secure and Realm register accesses:

Secure Restricted Access. Controls Secure access to error records and interrupt configuration registers in the error record group.

SRA	Meaning
0b00	Secure access is disabled. All error record, ERR<irq>CR<m>, and ERRIRQSR registers are RAZ/WI to Secure accesses.
0b01	Secure read access is enabled. Secure writes are ignored.
0b11	Secure read/write access is allowed.

All other values are reserved.

When Secure access to error records is disabled, a Secure read of ERRGSR will return the error record status for the error records that cannot be accessed.

When Secure access is fully or partially disabled, the effect on Secure accesses to IMPLEMENTATION DEFINED registers is IMPLEMENTATION DEFINED.

Note

Secure access to error records is enabled from reset.

The reset behavior of this field is:

On an Error recovery reset, this field resets to 3.

Otherwise:

NSRA, bits [1:0]

Non-secure Restricted Access. Controls Non-secure access to error records and interrupt configuration registers in the error record group.

NSRA	Meaning
0b00	Non-secure access is disabled. All error record, ERR<irq>CR<m>, and ERRIRQSR registers are RAZ/WI to Non-secure accesses.
0b01	Non-secure read access is enabled. Non-secure writes are ignored.
0b11	Non-secure read/write access is allowed. If the error record group supports MSIs, generated MSIs are always Non-secure.

All other values are reserved.

When Non-secure access to error records is disabled, a Non-secure read of ERRGSR will return the error record status for the error records that cannot be accessed.

When Non-secure access is fully or partially disabled, the effect on Non-secure accesses to IMPLEMENTATION DEFINED registers is IMPLEMENTATION DEFINED.

Note

Non-secure access to error records is enabled from reset.

If FEAT_RME is implemented and ERRACR.{RLRA, SRA} are not implemented, then ERRACR.NSRA applies to all Security states other than Root.

The reset behavior of this field is:

On an Error recovery reset, this field resets to 3.

Accessing ERRACR

ERRACR can be accessed through the external debug interface:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IMPLEMENTATION DEFINED
RAO	RES0																									RLRA		SRA		NSRA

ERRACR, Access Configuration Register

Purpose

Configuration

Attributes

Field descriptions

IMPLEMENTATION DEFINED, bits [63:32]

Bit [31]

Bits [30:6]

RLRA, bits [5:4]
When FEAT_RME is implemented and the error record group allows configuration of Secure and Realm register accesses:

Otherwise:

SRA, bits [3:2]
When Secure state is implemented, FEAT_RME is implemented and the error record group allows configuration of Secure and Realm register accesses:

Otherwise:

NSRA, bits [1:0]

Accessing ERRACR

ERRACR can be accessed through the external debug interface:

ERRACR, Access Configuration Register

Purpose

Configuration

Attributes

Field descriptions

IMPLEMENTATION DEFINED, bits [63:32]

Bit [31]

Bits [30:6]

RLRA, bits [5:4]When FEAT_RME is implemented and the error record group allows configuration of Secure and Realm register accesses:

Otherwise:

SRA, bits [3:2]When Secure state is implemented, FEAT_RME is implemented and the error record group allows configuration of Secure and Realm register accesses:

Otherwise:

NSRA, bits [1:0]

Accessing ERRACR

ERRACR can be accessed through the external debug interface:

RLRA, bits [5:4]
When FEAT_RME is implemented and the error record group allows configuration of Secure and Realm register accesses:

SRA, bits [3:2]
When Secure state is implemented, FEAT_RME is implemented and the error record group allows configuration of Secure and Realm register accesses: