GICC_IIDR, CPU Interface Identification Register

The GICC_IIDR characteristics are:

Purpose

Provides information about the implementer and revision of the CPU interface.

This register is present only when FEAT_GICv3_LEGACY is implemented. Otherwise, direct accesses to GICC_IIDR are RES0.

GICC_IIDR is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ProductID												Architecture_version				Revision				Implementer

Product Identifier.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

The version of the GIC architecture that is implemented.

The value of this field is an IMPLEMENTATION DEFINED choice of:

Architecture_version	Meaning
0b0001	GICv1.
0b0010	GICv2.
0b0011	FEAT_GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1.
0b0100	FEAT_GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1.

Other values are reserved.

Access to this field is RO.

Revision number for the CPU interface.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Contains the JEP106 code of the company that implemented the CPU interface.

Bits [11:8] are the JEP106 continuation code of the implementer. For an Arm implementation, this field is 0x4.
Bit [7] is always 0.
Bits [6:0] are the JEP106 identity code of the implementer. For an Arm implementation, bits [7:0] are therefore 0x3B.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Component	Offset	Instance
GIC CPU interface	0x00FC	GICC_IIDR

This interface is accessible as follows:

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6