GICD_ICACTIVER<n>E, Interrupt Clear-Active Registers (extended SPI range), n = 0 - 31

The GICD_ICACTIVER<n>E characteristics are:

Purpose

Removes the active state from the corresponding SPI in the extended SPI range.

This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICD_ICACTIVER<n>E are RES0.

When GICD_TYPER.ESPI==0, these registers are RES0.

When GICD_TYPER.ESPI==1, the number of implemented GICD_ICACTIVER<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.

GICD_ICACTIVER<n>E is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Clear_active_bit31	Clear_active_bit30	Clear_active_bit29	Clear_active_bit28	Clear_active_bit27	Clear_active_bit26	Clear_active_bit25	Clear_active_bit24	Clear_active_bit23	Clear_active_bit22	Clear_active_bit21	Clear_active_bit20	Clear_active_bit19	Clear_active_bit18	Clear_active_bit17	Clear_active_bit16	Clear_active_bit15	Clear_active_bit14	Clear_active_bit13	Clear_active_bit12	Clear_active_bit11	Clear_active_bit10	Clear_active_bit9	Clear_active_bit8	Clear_active_bit7	Clear_active_bit6	Clear_active_bit5	Clear_active_bit4	Clear_active_bit3	Clear_active_bit2	Clear_active_bit1	Clear_active_bit0

For the extended SPIs, removes the active state to interrupt number x. Reads and writes have the following behavior:

Clear_active_bit<x>	Meaning
0b0	If read, indicates that the corresponding interrupt is not active, and is not active and pending. If written, has no effect.
0b1	If read, indicates that the corresponding interrupt is active, or is active and pending. If written, deactivates the corresponding interrupt, if the interrupt is active. If the interrupt is already deactivated, the write has no effect.

Clear_active_bit<x>

Meaning

0b0

If read, indicates that the corresponding interrupt is not active, and is not active and pending.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is active, or is active and pending.

If written, deactivates the corresponding interrupt, if the interrupt is active. If the interrupt is already deactivated, the write has no effect.

The reset behavior of this field is:

For INTID m, when DIV and MOD are the integer division and modulo operations:

The corresponding GICD_ICACTIVER<n>E number, n, is given by n = (m-4096) DIV 32.
The offset of the required GICD_ICACTIVER<n>E is (0x1C00 + (4*n)).
The bit number of the required group modifier bit in this register is (m-4096) MOD 32.

When affinity routing is not enabled for the Security state of an interrupt in GICD_ICACTIVER<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

Component	Frame	Offset	Instance
GIC Distributor	Dist_base	0x1C00 + (4 * n)	GICD_ICACTIVER<n>E

Accesses on this interface are RW.

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6