GICR_ICACTIVER<n>E

Clear_active_bit<x>	Meaning
0b0	If read, indicates that the corresponding interrupt is not active, and is not active and pending. If written, has no effect.
0b1	If read, indicates that the corresponding interrupt is active, or is active and pending. If written, deactivates the corresponding interrupt, if the interrupt is active. If the interrupt is already deactivated, the write has no effect.

Clear_active_bit<x>

Meaning

0b0

If read, indicates that the corresponding interrupt is not active, and is not active and pending.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is active, or is active and pending.

If written, deactivates the corresponding interrupt, if the interrupt is active. If the interrupt is already deactivated, the write has no effect.

The reset behavior of this field is:

Additional information

For INTID m, when DIV and MOD are the integer division and modulo operations:

The corresponding GICR_ICACTIVER<n>E number, n, is given by n = (m-1024) DIV 32.
The offset of the required GICR_ICACTIVER<n>E is (0x200 + (4*n)).
The bit number of the required group modifier bit in this register is (m-1024) MOD 32.

Accessing GICR_ICACTIVER<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICR_ICACTIVER<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.

GICR_ICACTIVER<n>E can be accessed through the memory-mapped interfaces:

Component	Frame	Offset	Instance
GIC Redistributor	SGI_base	0x0380 + (4 * n)	GICR_ICACTIVER<n>E

Component

Frame

Offset

Instance

GIC Redistributor

SGI_base

0x0380 + (4 * n)

GICR_ICACTIVER<n>E

GICR_ICACTIVER<n>E, Interrupt Clear-Active Registers, n = 1 - 2