GICR_INMIR0, Non-maskable Interrupt Register 0

The GICR_INMIR0 characteristics are:

Purpose

Controls whether the corresponding SGI or PPI has the non-maskable property.

Configuration

This register is present only when FEAT_GICv3_NMI is implemented. Otherwise, direct accesses to GICR_INMIR0 are RES0.

When GICD_TYPER.NMI is 0, this register is RES0.

A copy of this register is provided for each Redistributor.

Attributes

GICR_INMIR0 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
nmi31nmi30nmi29nmi28nmi27nmi26nmi25nmi24nmi23nmi22nmi21nmi20nmi19nmi18nmi17nmi16nmi15nmi14nmi13nmi12nmi11nmi10nmi9nmi8nmi7nmi6nmi5nmi4nmi3nmi2nmi1nmi0

nmi<x>, bit [x], for x = 31 to 0

Non-maskable property.

nmi<x>Meaning
0b0

Interrupt does not have the non-maskable property.

0b1

Interrupt has the non-maskable property.

The reset behavior of this field is:

Additional information

If affinity routing is disabled for the Security state of an interrupt, the bit is RES0.

This bit is RES0 when the corresponding interrupt is configured as Group 0.

Accessing GICR_INMIR0

Bits corresponding to unimplemented interrupts are RAZ/WI.

When GICD_CTLR.DS==0, bits corresponding to Group 0 and Secure Group 1 interrupts are RAZ/WI to Non-secure accesses.

Note

Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.

GICR_INMIR0 can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorSGI_base0x0F80GICR_INMIR0

Accesses on this interface are RW.


26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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