TRBPIDR0, Peripheral Identification Register 0

The TRBPIDR0 characteristics are:

Purpose

Provides discovery information about the component.

For additional information, see the CoreSight Architecture Specification.

TRBPIDR0 is in the Core power domain.

This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBPIDR0 are RES0.

TRBPIDR0 is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								PART_0

Reserved, RES0.

Part number, bits [7:0].

The part number is selected by the designer of the component, and is stored in TRBPIDR1.PART_1 and TRBPIDR0.PART_0.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Component	Offset	Instance
TRBE	0xFE0	TRBPIDR0

This interface is accessible as follows:

When DoubleLockStatus() or !IsCorePowered(), accesses to this register generate an error response.
Otherwise, accesses to this register are RO.

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6