The TRCCIDR2 characteristics are:
Provides discovery information about the component.
For additional information, see the CoreSight Architecture Specification.
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCCIDR2 are RES0.
TRCCIDR2 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_2 |
Reserved, RES0.
Component identification preamble, segment 2.
Reads as 0x05.
Access to this field is RO.
External debugger accesses to this register are unaffected by the OS Lock.
Component | Offset | Instance |
---|---|---|
ETE | 0xFF8 | TRCCIDR2 |
This interface is accessible as follows:
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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