The TRCDEVAFF characteristics are:
For additional information, see the CoreSight Architecture Specification.
Reads the same value as the MPIDR_EL1 register for the PE that this trace unit has affinity with.
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCDEVAFF are RES0.
TRCDEVAFF is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPIDR_EL1 | |||||||||||||||||||||||||||||||
| MPIDR_EL1 | |||||||||||||||||||||||||||||||
Read-only copy of MPIDR_EL1, as seen from the highest implemented Exception level.
External debugger accesses to this register are unaffected by the OS Lock.
| Component | Offset | Instance |
|---|---|---|
| ETE | 0xFA8 | TRCDEVAFF |
This interface is accessible as follows:
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.