The PMMIR characteristics are:
Describes Performance Monitors parameters specific to the implementation.
This register is present only when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3p4 is implemented. Otherwise, direct accesses to PMMIR are RES0.
PMMIR is in the Core power domain.
PMMIR is a:
This register is part of the PMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | SME | EDGE | THWIDTH | BUS_WIDTH | BUS_SLOTS | SLOTS | |||||||||||||||||||||||||
Reserved, RES0.
PMUv3 for SME. Adds support for the Streaming SVE mode filter.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SME | Meaning |
|---|---|
| 0b0 |
FEAT_PMUv3_SME is not implemented. |
| 0b1 |
FEAT_PMUv3_SME is implemented. |
Access to this field is RO.
PMU event edge detection. With PMMIR_EL1.THWIDTH, indicates implementation of event counter thresholding features.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EDGE | Meaning |
|---|---|
| 0b0000 |
FEAT_PMUv3_EDGE is not implemented. |
| 0b0001 |
FEAT_PMUv3_EDGE is implemented. |
| 0b0010 |
As 0b0001, and adds support for threshold value linking between a pair of counters. |
All other values are reserved.
If FEAT_PMUv3_TH is not implemented, the only permitted value is 0b0000.
FEAT_PMUv3_EDGE implements the functionality identified by the value 0b0001.
FEAT_PMUv3_TH2 implements the functionality identified by the value 0b0010.
Access to this field is RO.
PMEVTYPER<n>_EL0.TH width. Indicates implementation of the FEAT_PMUv3_TH feature, and, if implemented, the size of the PMEVTYPER<n>_EL0.TH field.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| THWIDTH | Meaning |
|---|---|
| 0b0000 |
FEAT_PMUv3_TH is not implemented. |
| 0b0001 |
1 bit. PMEVTYPER<n>_EL0.TH[11:1] are RES0. |
| 0b0010 |
2 bits. PMEVTYPER<n>_EL0.TH[11:2] are RES0. |
| 0b0011 |
3 bits. PMEVTYPER<n>_EL0.TH[11:3] are RES0. |
| 0b0100 |
4 bits. PMEVTYPER<n>_EL0.TH[11:4] are RES0. |
| 0b0101 |
5 bits. PMEVTYPER<n>_EL0.TH[11:5] are RES0. |
| 0b0110 |
6 bits. PMEVTYPER<n>_EL0.TH[11:6] are RES0. |
| 0b0111 |
7 bits. PMEVTYPER<n>_EL0.TH[11:7] are RES0. |
| 0b1000 |
8 bits. PMEVTYPER<n>_EL0.TH[11:8] are RES0. |
| 0b1001 |
9 bits. PMEVTYPER<n>_EL0.TH[11:9] are RES0. |
| 0b1010 |
10 bits. PMEVTYPER<n>_EL0.TH[11:10] are RES0. |
| 0b1011 |
11 bits. PMEVTYPER<n>_EL0.TH[11] is RES0. |
| 0b1100 |
12 bits. |
All other values are reserved.
If FEAT_PMUv3_TH is not implemented, this field is zero.
Otherwise, the largest value that can be written to PMEVTYPER<n>_EL0.TH is 2(PMMIR.THWIDTH) minus one.
Access to this field is RO.
Bus width. Indicates the number of bytes each BUS_ACCESS event relates to. Encoded as Log2(number of bytes), plus one.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| BUS_WIDTH | Meaning |
|---|---|
| 0b0000 |
The information is not available. |
| 0b0011 |
Four bytes. |
| 0b0100 |
8 bytes. |
| 0b0101 |
16 bytes. |
| 0b0110 |
32 bytes. |
| 0b0111 |
64 bytes. |
| 0b1000 |
128 bytes. |
| 0b1001 |
256 bytes. |
| 0b1010 |
512 bytes. |
| 0b1011 |
1024 bytes. |
| 0b1100 |
2048 bytes. |
All other values are reserved.
Each transfer is up to this number of bytes. An access might be smaller than the bus width.
When this field is nonzero, each access counted by BUS_ACCESS is at most BUS_WIDTH bytes. An implementation might treat a wide bus as multiple narrower buses, such that a wide access on the bus increments the BUS_ACCESS counter by more than one.
Access to this field is RO.
Bus count. The largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle.
When this field is nonzero, the largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle is BUS_SLOTS.
If the bus count information is not available, this field will read as zero.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Operation width. The largest value by which the STALL_SLOT event might increment in a single cycle. If the STALL_SLOT event is not implemented, this field might read as zero.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | SME | EDGE | THWIDTH | BUS_WIDTH | BUS_SLOTS | SLOTS | |||||||||||||||||||||||||
Reserved, RES0.
PMUv3 for SME. Adds support for the Streaming SVE mode filter.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SME | Meaning |
|---|---|
| 0b0 |
FEAT_PMUv3_SME is not implemented. |
| 0b1 |
FEAT_PMUv3_SME is implemented. |
Access to this field is RO.
PMU event edge detection. With PMMIR_EL1.THWIDTH, indicates implementation of event counter thresholding features.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EDGE | Meaning |
|---|---|
| 0b0000 |
FEAT_PMUv3_EDGE is not implemented. |
| 0b0001 |
FEAT_PMUv3_EDGE is implemented. |
| 0b0010 |
As 0b0001, and adds support for threshold value linking between a pair of counters. |
All other values are reserved.
If FEAT_PMUv3_TH is not implemented, the only permitted value is 0b0000.
FEAT_PMUv3_EDGE implements the functionality identified by the value 0b0001.
FEAT_PMUv3_TH2 implements the functionality identified by the value 0b0010.
Access to this field is RO.
PMEVTYPER<n>_EL0.TH width. Indicates implementation of the FEAT_PMUv3_TH feature, and, if implemented, the size of the PMEVTYPER<n>_EL0.TH field.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| THWIDTH | Meaning |
|---|---|
| 0b0000 |
FEAT_PMUv3_TH is not implemented. |
| 0b0001 |
1 bit. PMEVTYPER<n>_EL0.TH[11:1] are RES0. |
| 0b0010 |
2 bits. PMEVTYPER<n>_EL0.TH[11:2] are RES0. |
| 0b0011 |
3 bits. PMEVTYPER<n>_EL0.TH[11:3] are RES0. |
| 0b0100 |
4 bits. PMEVTYPER<n>_EL0.TH[11:4] are RES0. |
| 0b0101 |
5 bits. PMEVTYPER<n>_EL0.TH[11:5] are RES0. |
| 0b0110 |
6 bits. PMEVTYPER<n>_EL0.TH[11:6] are RES0. |
| 0b0111 |
7 bits. PMEVTYPER<n>_EL0.TH[11:7] are RES0. |
| 0b1000 |
8 bits. PMEVTYPER<n>_EL0.TH[11:8] are RES0. |
| 0b1001 |
9 bits. PMEVTYPER<n>_EL0.TH[11:9] are RES0. |
| 0b1010 |
10 bits. PMEVTYPER<n>_EL0.TH[11:10] are RES0. |
| 0b1011 |
11 bits. PMEVTYPER<n>_EL0.TH[11] is RES0. |
| 0b1100 |
12 bits. |
All other values are reserved.
If FEAT_PMUv3_TH is not implemented, this field is zero.
Otherwise, the largest value that can be written to PMEVTYPER<n>_EL0.TH is 2(PMMIR.THWIDTH) minus one.
Access to this field is RO.
Bus width. Indicates the number of bytes each BUS_ACCESS event relates to. Encoded as Log2(number of bytes), plus one.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| BUS_WIDTH | Meaning |
|---|---|
| 0b0000 |
The information is not available. |
| 0b0011 |
Four bytes. |
| 0b0100 |
8 bytes. |
| 0b0101 |
16 bytes. |
| 0b0110 |
32 bytes. |
| 0b0111 |
64 bytes. |
| 0b1000 |
128 bytes. |
| 0b1001 |
256 bytes. |
| 0b1010 |
512 bytes. |
| 0b1011 |
1024 bytes. |
| 0b1100 |
2048 bytes. |
All other values are reserved.
Each transfer is up to this number of bytes. An access might be smaller than the bus width.
When this field is nonzero, each access counted by BUS_ACCESS is at most BUS_WIDTH bytes. An implementation might treat a wide bus as multiple narrower buses, such that a wide access on the bus increments the BUS_ACCESS counter by more than one.
Access to this field is RO.
Bus count. The largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle.
When this field is nonzero, the largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle is BUS_SLOTS.
If the bus count information is not available, this field will read as zero.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Operation width. The largest value by which the STALL_SLOT event might increment in a single cycle. If the STALL_SLOT event is not implemented, this field might read as zero.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
If the Core power domain is off or in a low-power state, access to this register returns an Error.
Accesses to this register use the following encodings:
[63:0] Accessible at offset 0xE40 from PMU
[31:0] Accessible at offset 0xE40 from PMU
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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