The PMSSCR_EL1 characteristics are:
Holds status information about the captured counters and provides a mechanism for software to initiate a sample.
External register PMSSCR_EL1 bits [63:0] are architecturally mapped to AArch64 System register PMSSCR_EL1[63:0].
This register is present only when FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMSSCR_EL1 are RES0.
PMSSCR_EL1 is a 64-bit register.
This register is part of the PMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | NC | ||||||||||||||||||||||||||||||
| RES0 | SS | ||||||||||||||||||||||||||||||
Reserved, RES0.
No Capture. Indicates whether the PMU counters have been captured.
| NC | Meaning |
|---|---|
| 0b0 |
PMU counters captured. |
| 0b1 |
PMU counters not captured. |
The reset behavior of this field is:
Reserved, RES0.
Snapshot Capture and Status.
| SS | Meaning |
|---|---|
| 0b0 |
On a read, the Capture event has completed. |
| 0b1 | On a read, the Capture event has not completed. On a write, request a Capture event. |
A write of 0 to this field is ignored.
It is CONSTRAINED UNPREDICTABLE whether a Capture event has completed if this field is modified when the Capture event is ongoing.
The reset behavior of this field is:
Accessing this field has the following behavior:
Accesses to this register use the following encodings:
Accessible at offset 0xE30 from PMU
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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