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DBGBXVR<n>, Debug Breakpoint Extended Value Registers, n = 0 - 15

The DBGBXVR<n> characteristics are:

Purpose

Holds a value for use in breakpoint matching, to support VMID matching. Used in conjunction with a control register DBGBCR<n> and a value register DBGBVR<n>, where EL2 is implemented and breakpoint n supports Context matching.

Configuration

AArch32 System register DBGBXVR<n> bits [31:0] are architecturally mapped to AArch64 System register DBGBVR<n>_EL1[63:32].

AArch32 System register DBGBXVR<n> bits [31:0] are architecturally mapped to External register DBGBVR<n>_EL1[63:32].

This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to DBGBXVR<n> are UNDEFINED.

How this register is interpreted depends on the value of DBGBCR<n>.BT.

For other values of DBGBCR<n>.BT, this register is RES0.

Accesses to this register are UNDEFINED in any of the following cases:

For more information, see the description of the DBGDIDR.CTX_CMPs field.

Attributes

DBGBXVR<n> is a 32-bit register.

Field descriptions

When DBGBCR<n>.BT IN {0b10xx} and EL2 is implemented:

313029282726252423222120191817161514131211109876543210
RES0VMID[15:8]VMID[7:0]

Bits [31:16]

Reserved, RES0.

VMID[15:8], bits [15:8]
When FEAT_VMID16 is implemented and VTCR_EL2.VS == 1:

Extension to VMID[7:0]. For more information, see VMID[7:0].

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

VMID[7:0], bits [7:0]

VMID value for comparison. The VMID is 8 bits when any of the following are true:

The reset behavior of this field is:

When DBGBCR<n>.BT IN {0b11xx} and EL2 is implemented:

313029282726252423222120191817161514131211109876543210
ContextID2

ContextID2, bits [31:0]
When FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented:

Context ID value for comparison against CONTEXTIDR_EL2.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Accessing DBGBXVR<n>

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} ; Where m = 0-15

coprocopc1CRnCRmopc2
0b11100b0000b0001m[3:0]0b001

integer m = UInt(CRm<3:0>); if m >= NUM_BREAKPOINTS then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else R[t] = DBGBXVR[m]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else R[t] = DBGBXVR[m]; elsif PSTATE.EL == EL3 then if DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else R[t] = DBGBXVR[m];

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} ; Where m = 0-15

coprocopc1CRnCRmopc2
0b11100b0000b0001m[3:0]0b001

integer m = UInt(CRm<3:0>); if m >= NUM_BREAKPOINTS then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBXVR[m] = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBXVR[m] = R[t]; elsif PSTATE.EL == EL3 then if DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBXVR[m] = R[t];

AArch32 Registers
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26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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