DBGBVR<n>

Holds a virtual address, or a VMID and/or a context ID, for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR<n>_EL1.

Configuration

AArch64 System register DBGBVR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGBVR<n>[31:0].

AArch64 System register DBGBVR<n>_EL1 bits [63:32] are architecturally mapped to AArch32 System register DBGBXVR<n>[31:0].

AArch64 System register DBGBVR<n>_EL1 bits [63:0] are architecturally mapped to External register DBGBVR<n>_EL1[63:0].

If breakpoint n is not implemented then accesses to this register are UNDEFINED.

Attributes

Field descriptions

When DBGBCR<n>_EL1.BT IN {0b000x}:

RESS[14:8], bits [63:57]

Bits[56:53]
When FEAT_LVA3 is implemented:

VA[56:53], bits [3:0] of bits [56:53]

Otherwise:

RESS[7:4], bits [3:0] of bits [56:53]

Bits[52:49]
When FEAT_LVA is implemented:

VA[52:49], bits [3:0] of bits [52:49]

Otherwise:

RESS[3:0], bits [3:0] of bits [52:49]

VA[48:2], bits [48:2]

Bits [1:0]

When DBGBCR<n>_EL1.BT IN {0b001x}:

Bits [63:32]

ContextID, bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b011x}:

Bits [63:32]

ContextID, bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b100x} and EL2 is implemented:

Bits [63:48]

VMID[15:8], bits [47:40]
When FEAT_VMID16 is implemented, VTCR_EL2.VS == 1 and EL2 is using AArch64:

Otherwise:

VMID[7:0], bits [39:32]

Bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b101x} and EL2 is implemented:

Bits [63:48]

VMID[15:8], bits [47:40]
When FEAT_VMID16 is implemented, VTCR_EL2.VS == 1 and EL2 is using AArch64:

Otherwise:

VMID[7:0], bits [39:32]

ContextID, bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b110x}, EL2 is implemented and (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented):

ContextID2, bits [63:32]

Bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b111x}, EL2 is implemented and (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented):

ContextID2, bits [63:32]

ContextID, bits [31:0]

Accessing DBGBVR<n>_EL1

When FEAT_Debugv8p9 is implemented, a PE is permitted to support up to 64 implemented breakpoints.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, DBGBVR<m>_EL1 ; Where m = 0-15

op0	op1	CRn	CRm	op2
0b10	0b000	0b0000	m[3:0]	0b100

integer m = UInt(CRm<3:0>); if (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_BREAKPOINTS) || (IsFeatureImplemented(FEAT_Debugv8p9) && m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16) >= NUM_BREAKPOINTS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.DBGBVRn_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then X[t, 64] = DBGBVR_EL1[m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)]; else X[t, 64] = DBGBVR_EL1[m]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then X[t, 64] = DBGBVR_EL1[m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)]; else X[t, 64] = DBGBVR_EL1[m]; elsif PSTATE.EL == EL3 then if OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then X[t, 64] = DBGBVR_EL1[m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)]; else X[t, 64] = DBGBVR_EL1[m];

MSR DBGBVR<m>_EL1, <Xt> ; Where m = 0-15

op0	op1	CRn	CRm	op2
0b10	0b000	0b0000	m[3:0]	0b100

integer m = UInt(CRm<3:0>); if (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_BREAKPOINTS) || (IsFeatureImplemented(FEAT_Debugv8p9) && m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16) >= NUM_BREAKPOINTS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.DBGBVRn_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then DBGBVR_EL1[m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)] = X[t, 64]; else DBGBVR_EL1[m] = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then DBGBVR_EL1[m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)] = X[t, 64]; else DBGBVR_EL1[m] = X[t, 64]; elsif PSTATE.EL == EL3 then if OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then DBGBVR_EL1[m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)] = X[t, 64]; else DBGBVR_EL1[m] = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESS[14:8]							Bits[56:53]				Bits[52:49]				VA[48:2]
VA[48:2]																														RES0

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
ContextID

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
ContextID

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																VMID[15:8]								VMID[7:0]
RES0

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																VMID[15:8]								VMID[7:0]
ContextID

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ContextID2
RES0

DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 - 63

Purpose

Configuration

Attributes

Field descriptions

When DBGBCR<n>_EL1.BT IN {0b000x}:

RESS[14:8], bits [63:57]

Bits[56:53]When FEAT_LVA3 is implemented:

VA[56:53], bits [3:0] of bits [56:53]

Otherwise:

RESS[7:4], bits [3:0] of bits [56:53]

Bits[52:49]When FEAT_LVA is implemented:

VA[52:49], bits [3:0] of bits [52:49]

Otherwise:

RESS[3:0], bits [3:0] of bits [52:49]

VA[48:2], bits [48:2]

Bits [1:0]

When DBGBCR<n>_EL1.BT IN {0b001x}:

Bits [63:32]

ContextID, bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b011x}:

Bits [63:32]

ContextID, bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b100x} and EL2 is implemented:

Bits [63:48]

VMID[15:8], bits [47:40]When FEAT_VMID16 is implemented, VTCR_EL2.VS == 1 and EL2 is using AArch64:

Otherwise:

VMID[7:0], bits [39:32]

Bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b101x} and EL2 is implemented:

Bits [63:48]

VMID[15:8], bits [47:40]When FEAT_VMID16 is implemented, VTCR_EL2.VS == 1 and EL2 is using AArch64:

Otherwise:

VMID[7:0], bits [39:32]

ContextID, bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b110x}, EL2 is implemented and (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented):

ContextID2, bits [63:32]

Bits [31:0]

When DBGBCR<n>_EL1.BT IN {0b111x}, EL2 is implemented and (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented):

ContextID2, bits [63:32]

ContextID, bits [31:0]

Accessing DBGBVR<n>_EL1

MRS <Xt>, DBGBVR<m>_EL1 ; Where m = 0-15

MSR DBGBVR<m>_EL1, <Xt> ; Where m = 0-15

Bits[56:53]
When FEAT_LVA3 is implemented:

Bits[52:49]
When FEAT_LVA is implemented:

VMID[15:8], bits [47:40]
When FEAT_VMID16 is implemented, VTCR_EL2.VS == 1 and EL2 is using AArch64:

VMID[15:8], bits [47:40]
When FEAT_VMID16 is implemented, VTCR_EL2.VS == 1 and EL2 is using AArch64: