ISR

Shows the pending status of the IRQ and FIQ interrupts and the SError exceptions.

Configuration

AArch32 System register ISR bits [31:0] are architecturally mapped to AArch64 System register ISR_EL1[31:0].

This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ISR are UNDEFINED.

Attributes

Field descriptions

Bits [31:9]

A, bit [8]

SError exception pending bit:

A	Meaning
0b0	No pending SError exception.
0b1	An SError exception is pending.

If all of the following apply then this field shows the pending status of virtual SError exceptions:

EL2 is implemented and enabled in the current Security state.
Any of the following apply:
- EL2 is using AArch64 and HCR_EL2.AMO is 1.
- EL2 is using AArch64, FEAT_DoubleFault2 is implemented, and the Effective value of HCRX_EL2.TMEA is 1.
- EL2 is using AArch32 and HCR.AMO is 1.
The PE is executing at EL1.

Otherwise, this field shows the pending status of physical SError exceptions.

If the SError exception is edge-triggered, this field is cleared to zero when the physical SError exception is taken.

I, bit [7]

IRQ pending bit. Indicates whether an IRQ interrupt is pending:

I	Meaning
0b0	No pending IRQ.
0b1	An IRQ interrupt is pending.

If all of the following apply then this field shows the pending status of virtual IRQ interrupts:

EL2 is implemented and enabled in the current Security state.
Any of the following apply:
- EL2 is using AArch64 and HCR_EL2.IMO is 1.
- EL2 is using AArch32 and HCR.IMO is 1.
The PE is executing at EL1.

Otherwise, this field shows the pending status of physical IRQ interrupts.

F, bit [6]

FIQ pending bit. Indicates whether an FIQ interrupt is pending.

F	Meaning
0b0	No pending FIQ.
0b1	An FIQ interrupt is pending.

If all of the following apply then this field shows the pending status of virtual FIQ interrupts:

EL2 is implemented and enabled in the current Security state.
Any of the following apply:
- EL2 is using AArch64 and HCR_EL2.FMO is 1.
- EL2 is using AArch32 and HCR.FMO is 1.
The PE is executing at EL1.

Otherwise, this field shows the pending status of physical FIQ interrupts.

Bits [5:0]

Accessing ISR

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b1100	0b0001	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else R[t] = ISR; elsif PSTATE.EL == EL2 then R[t] = ISR; elsif PSTATE.EL == EL3 then R[t] = ISR;

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																							A	I	F	RES0

ISR, Interrupt Status Register

Purpose