AT S1E0W, Address Translate Stage 1 EL0 Write

The AT S1E0W characteristics are:

Purpose

Performs stage 1 address translation from EL0, with permissions as if writing to the given virtual address from EL0, using the following translation regime:

When FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS} is a reserved value, this instruction is UNDEFINED at EL3.

Configuration

There are no configuration notes.

Attributes

AT S1E0W is a 64-bit System instruction.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Input address for translation
Input address for translation

Bits [63:0]

Input address for translation. The resulting address can be read from the PAR_EL1.

If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.

Executing AT S1E0W

Accesses to this instruction use the following encodings in the System instruction encoding space:

AT S1E0W, <Xt>

op0op1CRnCRmop2
0b010b0000b01110b10000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.AT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.ATS1E0W == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.AT(X[t, 64], TranslationStage_1, EL0, ATAccess_Write); elsif PSTATE.EL == EL2 then AArch64.AT(X[t, 64], TranslationStage_1, EL0, ATAccess_Write); elsif PSTATE.EL == EL3 then AArch64.AT(X[t, 64], TranslationStage_1, EL0, ATAccess_Write);


26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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