AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
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Proprietary Notice

SCR_EL3, Secure Configuration Register

The SCR_EL3 characteristics are:

Purpose

Defines the configuration of the current Security state. It specifies:

Configuration

This register is present only when EL3 is implemented. Otherwise, direct accesses to SCR_EL3 are UNDEFINED.

Attributes

SCR_EL3 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0NSEHACDBSEnHDBSSEnFGTEn2EnDSEDSERES0EnIDCP128RES0PFAREnTWERRTMEAEnFPMMECEnGPFD128EnAIEnPIEnSCTLR2EnTCR2EnRCWMASKEnEnTP2TRNDRGCSEnHXEnADEnEnAS0AMVOFFENTMETWEDEL
TWEDELTWEDEnECVEnFGTEnATAEnSCXTRES0FIENNMEAEASEEEL2APIAPKTERRTLORTWETWISTRWSIFHCESMDRES0RES1EAFIQIRQNS

Bit [63]

Reserved, RES0.

NSE, bit [62]
When FEAT_RME is implemented:

This field, evaluated with SCR_EL3.NS, selects the Security state of EL2 and lower Exception levels.

For a description of the values derived by evaluating NS and NSE together, see SCR_EL3.NS.

The reset behavior of this field is:


Otherwise:

The Effective value of this bit is 0b0.

Access to this field is RES0 .

HACDBSEn, bit [61]
When FEAT_HACDBS is implemented:

Enables access to the HACDBSBR_EL2 and HACDBSCONS_EL2 registers at EL2.

HACDBSEnMeaning
0b0

EL2 accesses to the specified registers are trapped to EL3.

0b1

This control does not cause any instructions to be trapped.

Traps are reported using an ESR_EL3.EC value of 0x18.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

HDBSSEn, bit [60]
When FEAT_HDBSS is implemented:

Enables access to HDBSSBR_EL2 and HDBSSPROD_EL2 registers at EL2.

HDBSSEnMeaning
0b0

EL2 accesses to the specified registers are trapped to EL3.

0b1

This control does not cause any instructions to be trapped.

Traps are reported using an ESR_EL3.EC value of 0x18.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

FGTEn2, bit [59]
When FEAT_FGT2 is implemented:

Fine-Grained Traps Enable 2.

When EL2 is implemented, enables the traps to EL2 controlled by HDFGRTR2_EL2, HDFGWTR2_EL2, HFGITR2_EL2, HFGRTR2_EL2, and HFGWTR2_EL2, and controls access to those registers.

FGTEn2Meaning
0b0

EL2 accesses to the specified registers are trapped to EL3. The values in these registers are treated as 0.

0b1

EL2 accesses to the specified registers are not trapped to EL3 by this mechanism.

Traps caused by accesses to the fine-grained trap registers are reported using an ESR_ELx.EC value of 0x18 and its associated ISS.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnDSE, bit [58]
When FEAT_E3DSE is implemented:

Enable for delegated SError exceptions pended by SCR_EL3.DSE.

EnDSEMeaning
0b0

Delegated SError exceptions pended by SCR_EL3.DSE are disabled.

0b1

Delegated SError exceptions pended by SCR_EL3.DSE are enabled.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

DSE, bit [57]
When FEAT_E3DSE is implemented:

Delegated SError exception for EL2, EL1, and EL0.

DSEMeaning
0b0

This mechanism is not making a delegated SError exception pending.

0b1

A delegated SError exception for EL2, EL1, and EL0 is pending because of this mechanism.

When EL2 is implemented and enabled in the current Security state, delegated SError exceptions pended by this field are affected by HCR_EL2.AMO and HCRX_EL2.TMEA.

Virtual SError exceptions pended by HCR_EL2.VSE have priority over delegated SError exceptions pended by this field.

This field is ignored by the PE and treated as zero when SCR_EL3.EnDSE is 0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [56]

Reserved, RES0.

EnIDCP128, bit [55]
When FEAT_SYSREG128 is implemented:

Enables access to IMPLEMENTATION DEFINED 128-bit System registers.

EnIDCP128Meaning
0b0

Accesses at EL2, EL1, EL0 to IMPLEMENTATION DEFINED 128-bit System registers are trapped to EL3 using an ESR_EL3.EC value of 0x14, unless the access generates a higher priority exception.

Disables the functionality of the 128-bit IMPLEMENTATION DEFINED System registers that are accessible at EL3.

0b1

No accesses are trapped by this control.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [54]

Reserved, RES0.

PFAREn, bit [53]
When FEAT_PFAR is implemented:

Enable access to Physical Fault Address Registers. When disabled, accesses to Physical Fault Address Registers generate a trap to EL3.

PFAREnMeaning
0b0

Accesses of the specified Physical Fault Address Registers at EL2 and EL1 are trapped to EL3, unless the instruction generates a higher priority exception.

0b1

This control does not cause any instructions to be trapped.

In AArch64 state, the instructions affected by this control are: MRS and MSR accesses to PFAR_EL1, PFAR_EL2, and PFAR_EL12.

Unless the instruction generates a higher priority exception, trapped instructions generate an exception to EL3.

Trapped instructions are reported using EC syndrome value 0x18.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TWERR, bit [52]
When FEAT_RASv2 is implemented:

Trap writes of Error Record registers. Enables a trap to EL3 on writes of Error Record registers.

TWERRMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Writes of the specified Error Record registers at EL2 and EL1 are trapped to EL3, unless the instruction generates a higher priority exception.

In AArch64 state, the instructions affected by this control are: MSR accesses to ERRSELR_EL1, ERXADDR_EL1, ERXCTLR_EL1, ERXMISC0_EL1, ERXMISC1_EL1, ERXMISC2_EL1, ERXMISC3_EL1, and ERXSTATUS_EL1.

In AArch32 state, the instructions affected by this control are: MCR accesses to ERRSELR, ERXADDR, ERXADDR2, ERXCTLR, ERXCTLR2, ERXMISC0, ERXMISC1, ERXMISC2, ERXMISC3, ERXMISC4, ERXMISC5, ERXMISC6, ERXMISC7, and ERXSTATUS.

Unless the instruction generates a higher priority exception, trapped instructions generate an exception to EL3.

Trapped AArch64 instructions are reported using EC syndrome value 0x18.

Trapped AArch32 instructions are reported using EC syndrome value 0x03.

Accessing this field has the following behavior:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TMEA, bit [51]
When FEAT_DoubleFault2 is implemented:

Trap Masked External Aborts. Controls whether a masked error exception at a lower Exception level is taken to EL3.

TMEAMeaning
0b0

Synchronous External abort exceptions and SError exceptions at EL2, EL1, and EL0 are unaffected by this mechanism. That is, these exceptions are not taken to EL3 unless routed to EL3 by another control.

0b1

When executing at Exception levels below EL3, all of the following apply:

  • When PSTATE.A is 1, synchronous External abort exceptions are taken to EL3, unless they are taken from EL1 or EL0 and routed to EL2 by another control.

  • Masked physical SError exceptions are taken to EL3, unless they are taken from EL1 or EL0 and and routed to EL2 by another control.

This field has no effect on the routing of virtual or delegated SError exceptions.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnFPM, bit [50]
When FEAT_FPMR is implemented:

Enables the following accesses to FPMR from EL2, EL1, and EL0 to EL3:

EnFPMMeaning
0b0

EL2, EL1, and EL0 accesses to FPMR are disabled and trapped to EL3.

0b1

This control does not cause any instructions to be trapped.

Traps are not taken if there is a higher priority exception generated by the access.

If EL3 is not implemented, the Effective value of this field is 0b1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

MECEn, bit [49]
When FEAT_MEC is implemented:

Enables access to the following EL2 MECID registers, from EL2:

Accesses to these registers are trapped and reported using an ESR_EL3.EC value of 0x18.

MECEnMeaning
0b0

EL2 accesses to any of the specified registers are trapped to EL3. The values of the specified registers are treated as 0 for all purposes other than direct reads or writes to the register from EL3.

0b1

This control does not cause any instructions to be trapped.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

GPF, bit [48]
When FEAT_RME is implemented:

Controls the reporting of Granule protection faults at EL0, EL1 and EL2.

GPFMeaning
0b0

This control does not cause exceptions to be routed from EL0, EL1 or EL2 to EL3.

0b1

GPFs at EL0, EL1 and EL2 are routed to EL3 and reported as Granule Protection Check exceptions.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

D128En, bit [47]
When FEAT_D128 is implemented:

128-bit System Register trap control. Enables access to 128-bit System Registers via MRRS, MSRR instructions.

D128EnMeaning
0b0

EL1 and EL2 accesses to the specified registers are disabled, and trapped to EL3.

0b1

This control does not cause any instructions to be trapped.

Traps are not taken if there is a higher priority exception generated by the access.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

AIEn, bit [46]
When FEAT_AIE is implemented:

MAIR2_ELx, AMAIR2_ELx Register access trap control.

AIEnMeaning
0b0

EL1 and EL2 accesses to the specificed registers are disabled, and trapped to EL3. The values in these registers are treated as 0.

0b1

This control does not cause any instructions to be trapped.

Traps are not taken if there is a higher priority exception generated by the access.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

PIEn, bit [45]
When FEAT_S1PIE is implemented, or FEAT_S2PIE is implemented, or FEAT_S1POE is implemented or FEAT_S2POE is implemented:

Permission Indirection, Overlay Register access trap control. Enables access to Permission Indirection and Overlay registers.

PIEnMeaning
0b0

EL0, EL1 and EL2 accesses to the specificed registers are disabled, and trapped to EL3. The values in these registers are treated as 0.

0b1

This control does not cause any instructions to be trapped.

Traps are not taken if there is a higher priority exception generated by the access.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SCTLR2En, bit [44]
When FEAT_SCTLR2 is implemented:

SCTLR2_ELx register trap control. Enables access to SCTLR2_EL1 and SCTLR2_EL2 registers.

SCTLR2EnMeaning
0b0

EL1 and EL2 accesses to SCTLR2_EL1 and SCTLR2_EL2 registers are disabled, and trapped to EL3. The values in these registers are treated as 0.

0b1

This control does not cause any instructions to be trapped.

Traps are reported using an ESR_EL3.EC value of 0x18.

Traps are not taken if there is a higher priority exception generated by the access.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TCR2En, bit [43]
When FEAT_TCR2 is implemented:

TCR2_ELx register trap control. Enables access to TCR2_EL1 and TCR2_EL2 registers.

TCR2EnMeaning
0b0

EL1 and EL2 accesses to TCR2_EL1 and TCR2_EL2 registers are disabled, and trapped to EL3. The values in these registers are treated as 0.

0b1

This control does not cause any instructions to be trapped.

Traps are reported using an ESR_EL3.EC value of 0x18.

Traps are not taken if there is a higher priority exception generated by the access.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

RCWMASKEn, bit [42]
When FEAT_THE is implemented:

RCW and RCWS Mask register trap control. Enables access to RCWMASK_EL1, RCWSMASK_EL1.

RCWMASKEnMeaning
0b0

EL1 and EL2 accesses to RCWMASK_EL1 and RCWSMASK_EL1 registers are disabled, and trapped to EL3.

0b1

This control does not cause any instructions to be trapped.

Traps for MRS, MSR access are reported using an ESR_EL3.EC value of 0x18.

Traps for MRRS, MSRR acceess are reported using an ESR_EL3.EC value of 0x14.

Traps are not taken if there is a higher priority exception generated by the access.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnTP2, bit [41]
When FEAT_SME is implemented:

Traps instructions executed at EL2, EL1, and EL0 that access TPIDR2_EL0 to EL3. The exception is reported using ESR_ELx.EC value 0x18.

EnTP2Meaning
0b0

This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped.

0b1

This control does not cause execution of any instructions to be trapped.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TRNDR, bit [40]
When FEAT_RNG_TRAP is implemented:

Controls trapping of reads of RNDR and RNDRRS. The exception is reported using ESR_ELx.EC value 0x18.

TRNDRMeaning
0b0

This control does not cause RNDR and RNDRRS to be trapped.

When FEAT_RNG is implemented:

When FEAT_RNG is not implemented:

0b1

ID_AA64ISAR0_EL1.RNDR returns the value 0b0001.

Any attempt to read RNDR or RNDRRS is trapped to EL3.

When FEAT_RNG is not implemented, Arm recommends that SCR_EL3.TRNDR is initialized before entering Exception levels below EL3 and not subsequently changed.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

GCSEn, bit [39]
When FEAT_GCS is implemented:

Guarded Control Stack enable. Controls access to the Guarded Control Stack registers from EL2, EL1, and EL0, and controls whether the Guarded Control Stack is enabled.

The Guarded Control Stack registers trapped by this mechanism are:

GCSEnMeaning
0b0

Trap read and write accesses to all Guarded Control Stack registers to EL3. All Guarded Control Stack behavior is disabled at EL2, EL1, and EL0.

0b1

This control does not cause any instructions to be trapped, and does not disable Guarded Control Stack behavior at EL2, EL1, or EL0.

Traps are reported using an ESR_EL3.EC value of 0x18.

Traps are not taken if there is a higher priority exception generated by the access.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

HXEn, bit [38]
When FEAT_HCX is implemented:

Enables access to the HCRX_EL2 register at EL2 from EL3.

HXEnMeaning
0b0

Accesses at EL2 to HCRX_EL2 are trapped to EL3.

0b1

This control does not cause any instructions to be trapped.

When EL3 is not implemented, the Effective value of this field is 1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

ADEn, bit [37]
When FEAT_LS64_ACCDATA is implemented:

Enables access to the ACCDATA_EL1 register at EL1 and EL2.

ADEnMeaning
0b0

Accesses to ACCDATA_EL1 at EL1 and EL2 are trapped to EL3, unless the accesses are trapped to EL2 by the EL2 fine-grained trap.

0b1

This control does not cause accesses to ACCDATA_EL1 to be trapped.

If the HFGWTR_EL2.nACCDATA_EL1 or HFGRTR_EL2.nACCDATA_EL1 traps are enabled, they take priority over this trap.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnAS0, bit [36]
When FEAT_LS64_ACCDATA is implemented:

Traps execution of an ST64BV0 instruction at EL0, EL1, or EL2 to EL3.

EnAS0Meaning
0b0

EL0 execution of an ST64BV0 instruction is trapped to EL3, unless it is trapped to EL1 by SCTLR_EL1.EnAS0, or to EL2 by either HCRX_EL2.EnAS0 or SCTLR_EL2.EnAS0.

EL1 execution of an ST64BV0 instruction is trapped to EL3, unless it is trapped to EL2 by HCRX_EL2.EnAS0.

EL2 execution of an ST64BV0 instruction is trapped to EL3.

0b1

This control does not cause any instructions to be trapped.

A trap of an ST64BV0 instruction is reported using an ESR_ELx.EC value of 0x0A, with an ISS code of 0x0000001.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

AMVOFFEN, bit [35]
When FEAT_AMUv1p1 is implemented:

Activity Monitors Virtual Offsets Enable.

AMVOFFENMeaning
0b0

Accesses to AMEVCNTVOFF0<n>_EL2 and AMEVCNTVOFF1<n>_EL2 at EL2 are trapped to EL3. Indirect reads of the virtual offset registers are zero.

0b1

Accesses to AMEVCNTVOFF0<n>_EL2 and AMEVCNTVOFF1<n>_EL2 are not affected by this field.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TME, bit [34]
When FEAT_TME is implemented:

Enables access to the TSTART, TCOMMIT, TTEST and TCANCEL instructions at EL0, EL1 and EL2.

TMEMeaning
0b0

EL0, EL1 and EL2 accesses to TSTART, TCOMMIT, TTEST and TCANCEL instructions are UNDEFINED.

0b1

This control does not cause any instruction to be UNDEFINED.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TWEDEL, bits [33:30]
When FEAT_TWED is implemented:

TWE Delay. A 4-bit unsigned number that, when SCR_EL3.TWEDEn is 1, encodes the minimum delay in taking a trap of WFE* caused by SCR_EL3.TWE as 2(TWEDEL + 8) cycles.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TWEDEn, bit [29]
When FEAT_TWED is implemented:

TWE Delay Enable. Enables a configurable delayed trap of the WFE* instruction caused by SCR_EL3.TWE.

Traps are reported using an ESR_ELx.EC value of 0x01.

TWEDEnMeaning
0b0

The delay for taking the trap is IMPLEMENTATION DEFINED.

0b1

The delay for taking the trap is at least the number of cycles defined in SCR_EL3.TWEDEL.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

ECVEn, bit [28]
When FEAT_ECV is implemented:

ECV Enable. Enables access to the CNTPOFF_EL2 register.

ECVEnMeaning
0b0

EL2 accesses to CNTPOFF_EL2 are trapped to EL3, and the value of CNTPOFF_EL2 is treated as 0 for all purposes other than direct reads or writes to the register from EL3.

0b1

EL2 accesses to CNTPOFF_EL2 are not trapped to EL3 by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

FGTEn, bit [27]
When FEAT_FGT is implemented:

Fine-Grained Traps Enable. When EL2 is implemented, enables the traps to EL2 controlled by HAFGRTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGRTR_EL2, HFGITR_EL2, and HFGWTR_EL2, and controls access to those registers.

Note

If EL2 is not implemented but EL3 is implemented, FEAT_FGT implements the MDCR_EL3.TDCC traps.

FGTEnMeaning
0b0

EL2 accesses to HAFGRTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGRTR_EL2, HFGITR_EL2 and HFGWTR_EL2 registers are trapped to EL3, and the traps to EL2 controlled by those registers are disabled.

0b1

EL2 accesses to HAFGRTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGRTR_EL2, HFGITR_EL2 and HFGWTR_EL2 registers are not trapped to EL3 by this mechanism.

Traps caused by accesses to the fine-grained trap registers are reported using an ESR_ELx.EC value of 0x18 and its associated ISS.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

ATA, bit [26]
When FEAT_MTE2 is implemented:

Allocation Tag Access. Controls access to Allocation Tags, System registers for Memory tagging, and prevention of Tag checking, at EL2, EL1 and EL0.

ATAMeaning
0b0

Access to Allocation Tags is prevented at EL2, EL1, and EL0.

Accesses at EL1 and EL2 to GCR_EL1, RGSR_EL1, TFSR_EL1, TFSR_EL2 or TFSRE0_EL1 that are not UNDEFINED or trapped to a lower Exception level are trapped to EL3.

Accesses at EL2 using MRS or MSR with the register name TFSR_EL12 that are not UNDEFINED are trapped to EL3.

Memory accesses at EL2, EL1, and EL0 are not subject to a Tag Check operation.

0b1

This control does not prevent access to Allocation Tags at EL2, EL1, and EL0.

This control does not prevent Tag checking at EL2, EL1, and EL0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnSCXT, bit [25]
When FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented:

Enables access to the SCXTNUM_EL2, SCXTNUM_EL1, and SCXTNUM_EL0 registers.

EnSCXTMeaning
0b0

Accesses at EL0, EL1 and EL2 to SCXTNUM_EL0, SCXTNUM_EL1, or SCXTNUM_EL2 registers are trapped to EL3 if they are not trapped by a higher priority exception, and the values of these registers are treated as 0.

0b1

This control does not cause any accesses to be trapped, or register values to be treated as 0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [24:22]

Reserved, RES0.

FIEN, bit [21]
When FEAT_RASv1p1 is implemented:

Fault Injection enable. Trap accesses to the registers ERXPFGCDN_EL1, ERXPFGCTL_EL1, and ERXPFGF_EL1 from EL1 and EL2 to EL3, reported using an ESR_ELx.EC value of 0x18.

FIENMeaning
0b0

Accesses to the specified registers from EL1 and EL2 generate a Trap exception to EL3.

0b1

This control does not cause any instructions to be trapped.

If EL3 is not implemented, the Effective value of SCR_EL3.FIEN is 0b1.

If ERRIDR_EL1.NUM is zero, meaning no error records are implemented, or no error record accessible using System registers is owned by a node that implements the RAS Common Fault Injection Model Extension, then this bit might be RES0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NMEA, bit [20]
When FEAT_DoubleFault is implemented:

Non-maskable External Aborts. Controls whether PSTATE.A masks SError exceptions at EL3.

NMEAMeaning
0b0

SError exceptions are not taken at EL3 if PSTATE.A == 1.

0b1

SError exceptions are taken at EL3 regardless of the value of PSTATE.A.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EASE, bit [19]
When FEAT_DoubleFault is implemented:

External aborts to SError exception vector.

EASEMeaning
0b0

Synchronous External abort exceptions taken to EL3 are taken to the appropriate synchronous exception vector offset from VBAR_EL3.

0b1

Synchronous External abort exceptions taken to EL3 are taken to the appropriate SError exception vector offset from VBAR_EL3.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EEL2, bit [18]
When FEAT_SEL2 is implemented:

Secure EL2 Enable.

EEL2Meaning
0b0

All behaviors associated with Secure EL2 are disabled. All registers, including timer registers, defined by FEAT_SEL2 are UNDEFINED, and those timers are disabled.

0b1

All behaviors associated with Secure EL2 are enabled.

When the value of this bit is 1, then:

Note

If the Effective value of SCR_EL3.EEL2 is 0, then these operations executed in Secure EL1 using AArch32 are trapped to EL3.

A Secure only implementation that does not implement EL3 but implements EL2, behaves as if SCR_EL3.EEL2 == 1.

This bit is permitted to be cached in a TLB.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

API, bit [17]
When FEAT_PAuth is implemented:

Controls the use of the following instructions related to Pointer Authentication.

APIMeaning
0b0

The specified instructions are trapped to EL3, when the instructions are enabled, unless they are trapped to EL2 as a result of the higher priority HCR_EL2.API trap.

0b1

This control does not cause any instructions to be trapped.

Traps are reported using an ESR_ELx.EC value of 0x09.

An instruction is trapped only if Pointer Authentication is enabled for that instruction, for more information, see 'PAC generation and verification keys'.

Note

If FEAT_PAuth is implemented but EL3 is not implemented, the system behaves as if this bit is 1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

APK, bit [16]
When FEAT_PAuth is implemented:

Trap registers holding "key" values for Pointer Authentication. Traps accesses to the following registers, using an ESR_ELx.EC value of 0x18, from EL1 or EL2 to EL3 unless they are trapped to EL2 as a result of the HCR_EL2.APK bit or other traps:

APKMeaning
0b0

Access to the registers holding "key" values for pointer authentication from EL1 or EL2 are trapped to EL3 unless they are trapped to EL2 as a result of the HCR_EL2.APK bit or other traps.

0b1

This control does not cause any instructions to be trapped.

For more information, see 'PAC generation and verification keys'.

Note

If FEAT_PAuth is implemented but EL3 is not implemented, the system behaves as if this bit is 1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TERR, bit [15]
When FEAT_RAS is implemented:

Trap accesses of Error Record registers. Enables a trap to EL3 on accesses of Error Record registers.

TERRMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Accesses of the specified Error Record registers at EL2 and EL1 are trapped to EL3, unless the instruction generates a higher priority exception.

In AArch64 state, the instructions affected by this control are:

In AArch32 state, the instructions affected by this control are:

Unless the instruction generates a higher priority exception, trapped instructions generate an exception to EL3.

Trapped AArch64 instructions are reported using EC syndrome value 0x18.

Trapped AArch32 instructions are reported using EC syndrome value 0x03.

Accessing this field has the following behavior:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TLOR, bit [14]
When FEAT_LOR is implemented:

Trap LOR registers. Traps accesses to the LORSA_EL1, LOREA_EL1, LORN_EL1, LORC_EL1, and LORID_EL1 registers from EL1 and EL2 to EL3, unless the access has been trapped to EL2.

TLORMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

EL1 and EL2 accesses to the LOR registers that are not UNDEFINED are trapped to EL3, unless it is trapped HCR_EL2.TLOR.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TWE, bit [13]

Traps EL2, EL1, and EL0 execution of WFE instructions to EL3, from any Security state and both Execution states, reported using an ESR_ELx.EC value of 0x01.

When FEAT_WFxT is implemented, this trap also applies to the WFET instruction.

TWEMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Any attempt to execute a WFE instruction at any Exception level lower than EL3 is trapped to EL3, if the instruction would otherwise have caused the PE to enter a low-power state and it is not trapped by SCTLR.nTWE, HCR.TWE, SCTLR_EL1.nTWE, SCTLR_EL2.nTWE, or HCR_EL2.TWE.

In AArch32 state, the attempted execution of a conditional WFE instruction is only trapped if the instruction passes its condition code check.

Note

Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.

For more information about when WFE instructions can cause the PE to enter a low-power state, see 'Wait for Event mechanism and Send event'.

The reset behavior of this field is:

TWI, bit [12]

Traps EL2, EL1, and EL0 execution of WFI instructions to EL3, from any Security state and both Execution states, reported using an ESR_ELx.EC value of 0x01.

When FEAT_WFxT is implemented, this trap also applies to the WFIT instruction.

TWIMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Any attempt to execute a WFI instruction at any Exception level lower than EL3 is trapped to EL3, if the instruction would otherwise have caused the PE to enter a low-power state and it is not trapped by SCTLR.nTWI, HCR.TWI, SCTLR_EL1.nTWI, SCTLR_EL2.nTWI, or HCR_EL2.TWI.

In AArch32 state, the attempted execution of a conditional WFI instruction is only trapped if the instruction passes its condition code check.

Note

Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.

For more information about when WFI instructions can cause the PE to enter a low-power state, see 'Wait for Interrupt'.

The reset behavior of this field is:

ST, bit [11]

Traps Secure EL1 accesses to the Counter-timer Physical Secure timer registers to EL3, from AArch64 state only, reported using an ESR_ELx.EC value of 0x18.

STMeaning
0b0

Secure EL1 using AArch64 accesses to the CNTPS_TVAL_EL1, CNTPS_CTL_EL1, and CNTPS_CVAL_EL1 are trapped to EL3 when Secure EL2 is disabled. If Secure EL2 is enabled, the behavior is as if the value of this field was 0b1.

0b1

This control does not cause any instructions to be trapped.

Note

Accesses to the Counter-timer Physical Secure timer registers are always enabled at EL3. These registers are not accessible at EL0.

When FEAT_RME is implemented and Secure state is not implemented, this bit is RES0.

The reset behavior of this field is:

RW, bit [10]
When EL1 is capable of using AArch32 or EL2 is capable of using AArch32:

Execution state control for lower Exception levels.

RWMeaning
0b0

Lower levels are all AArch32.

0b1

The next lower level is AArch64.

If EL2 is present:

  • EL2 is AArch64.

  • EL2 controls EL1 and EL0 behaviors.

If EL2 is not present:

  • EL1 is AArch64.

  • EL0 is determined by the Execution state described in the current process state when executing at EL0.

If AArch32 state is supported by the implementation at EL1, SCR_EL3.NS == 1 and AArch32 state is not supported by the implementation at EL2, the Effective value of this bit is 1.

If AArch32 state is supported by the implementation at EL1, FEAT_SEL2 is implemented and SCR_EL3.{EEL2, NS} == {1, 0}, the Effective value of this bit is 1.

This bit is permitted to be cached in a TLB.

The reset behavior of this field is:


Otherwise:

Reserved, RAO/WI.

SIF, bit [9]

Secure instruction fetch. When the PE is in Secure state, this bit disables instruction execution from memory marked in the first stage of translation as being Non-secure.

SIFMeaning
0b0

Secure state instruction execution from memory marked in the first stage of translation as being Non-secure is permitted.

0b1

Secure state instruction execution from memory marked in the first stage of translation as being Non-secure is not permitted.

When FEAT_RME is implemented and Secure state is not implemented, this bit is RES0.

When FEAT_PAN3 is implemented, it is IMPLEMENTATION DEFINED whether SCR_EL3.SIF is also used to determine instruction access permission for the purpose of PAN.

This bit is permitted to be cached in a TLB.

The reset behavior of this field is:

HCE, bit [8]

Hypervisor Call instruction enable. Enables HVC instructions at EL3 and, if EL2 is enabled in the current Security state, at EL2 and EL1, in both Execution states, reported using an ESR_ELx.EC value of 0x00.

HCEMeaning
0b0

HVC instructions are UNDEFINED.

0b1

HVC instructions are enabled at EL3, EL2, and EL1.

Note

HVC instructions are always UNDEFINED at EL0 and, if Secure EL2 is disabled, at Secure EL1. Any resulting exception is taken from the current Exception level to the current Exception level.

If EL2 is not implemented, this bit is RES0.

The reset behavior of this field is:

SMD, bit [7]

Secure Monitor Call disable. Disables SMC instructions at EL1 and above, from any Security state and both Execution states, reported using an ESR_ELx.EC value of 0x00.

SMDMeaning
0b0

SMC instructions are enabled at EL3, EL2 and EL1.

0b1

SMC instructions are UNDEFINED.

Note

SMC instructions are always UNDEFINED at EL0. Any resulting exception is taken from the current Exception level to the current Exception level.

If HCR_EL2.TSC or HCR.TSC traps attempted EL1 execution of SMC instructions to EL2, that trap has priority over this disable.

The reset behavior of this field is:

Bit [6]

Reserved, RES0.

Bits [5:4]

Reserved, RES1.

EA, bit [3]

External Abort and SError exception routing.

EAMeaning
0b0

When executing at Exception levels below EL3, External aborts and SError exceptions are not taken to EL3.

In addition, when executing at EL3:

  • SError exceptions are not taken.

  • External aborts are taken to EL3.

0b1

When executing at any Exception level, External aborts and SError exceptions are taken to EL3.

This field has no effect on the routing of virtual or delegated SError exceptions.

For more information, see 'Asynchronous exception routing'.

The reset behavior of this field is:

FIQ, bit [2]

Physical FIQ Routing.

FIQMeaning
0b0

When executing at Exception levels below EL3, physical FIQ interrupts are not taken to EL3.

When executing at EL3, physical FIQ interrupts are not taken.

0b1

When executing at any Exception level, physical FIQ interrupts are taken to EL3.

For more information, see 'Asynchronous exception routing'.

The reset behavior of this field is:

IRQ, bit [1]

Physical IRQ Routing.

IRQMeaning
0b0

When executing at Exception levels below EL3, physical IRQ interrupts are not taken to EL3.

When executing at EL3, physical IRQ interrupts are not taken.

0b1

When executing at any Exception level, physical IRQ interrupts are taken to EL3.

For more information, see 'Asynchronous exception routing'.

The reset behavior of this field is:

NS, bit [0]
When FEAT_RME is implemented:

Non-secure bit. This field is used in combination with SCR_EL3.NSE to select the Security state of EL2 and lower Exception levels.

NSENSMeaning
0b00b0Secure.
0b00b1Non-secure.
0b10b0Reserved.
0b10b1Realm.

When Secure state is not implemented, SCR_EL3.NS is RES1 and its effective value is 1.

The reset behavior of this field is:


Otherwise:

Non-secure bit.

NSMeaning
0b0

Indicates that EL0 and EL1 are in Secure state.

When FEAT_SEL2 is implemented and SCR_EL3.EEL2 == 1, then EL2 is using AArch64 and in Secure state.

0b1

Indicates that Exception levels lower than EL3 are in Non-secure state, so memory accesses from those Exception levels cannot access Secure memory.

The reset behavior of this field is:

Accessing SCR_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SCR_EL3

op0op1CRnCRmop2
0b110b1100b00010b00010b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = SCR_EL3;

MSR SCR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b00010b00010b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then SCR_EL3 = X[t, 64];

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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