PMOVSSET

Allows software to set the unsigned overflow flags for the following counters to 1:

Configuration

AArch64 System register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMOVSSET[31:0].

AArch64 System register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMOVSR[31:0].

AArch64 System register PMOVSSET_EL0 bits [31:0] are architecturally mapped to External register PMU.PMOVSCLR_EL0[31:0].

AArch64 System register PMOVSSET_EL0 bits [31:0] are architecturally mapped to External register PMU.PMOVSSET_EL0[31:0].

AArch64 System register PMOVSSET_EL0 bits [63:32] are architecturally mapped to External register PMU.PMOVSCLR_EL0[63:32] when FEAT_PMUv3p9 is implemented or FEAT_PMUv3_EXT64 is implemented.

AArch64 System register PMOVSSET_EL0 bits [63:32] are architecturally mapped to External register PMU.PMOVSSET_EL0[63:32] when FEAT_PMUv3p9 is implemented or FEAT_PMUv3_EXT64 is implemented.

AArch64 System register PMOVSSET_EL0 bits [63:0] are architecturally mapped to External register PMU.PMOVS[63:0].

This register is present only when FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMOVSSET_EL0 are UNDEFINED.

Attributes

Field descriptions

Bits [63:33]

F<m>, bit [m+32], for m = 0
When FEAT_PMUv3_ICNTR is implemented:

Unsigned overflow flag for fixed-function counter <m> set. On writes, allows software to set the unsigned overflow flag for fixed-function counter <m> to 1. On reads, returns the unsigned overflow flag for fixed-function counter <m> overflow status.

F<m>	Meaning
0b0	Fixed-function counter <m> has not overflowed.
0b1	Fixed-function counter <m> has overflowed.

PMOVSSET_EL0.F0 holds the overflow status for PMICNTR_EL0.

Accessing this field has the following behavior:

This field reads-as-zero if all of the following are true:
- Any of the following are true:
  - EL3 is implemented and SCR_EL3.FGTEn2 == 0.
  - HDFGRTR2_EL2.nPMICFILTR_EL0 == 0.
- FEAT_FGT2 is implemented.
- EL2 is implemented and enabled in the current Security state.
- Accessed at EL1 or EL0.
- The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}.
Permitted reads and writes of this field are RAZ/WI if any of the following are true:
- All of the following are true:
  - EL3 is implemented.
  - MDCR_EL3.EnPM2 == 0.
  - Accessed at EL2, EL1, or EL0.
- All of the following are true:
  - PMUSERENR_EL0.UEN == 0 or PMUACR_EL1.F<m> == 0.
  - Accessed at EL0.
Permitted writes of this field are ignored if any of the following are true:
- All of the following are true:
  - EL3 is implemented and SCR_EL3.FGTEn2 == 0, or HDFGWTR2_EL2.nPMICFILTR_EL0 == 0.
  - FEAT_FGT2 is implemented.
  - EL2 is implemented and enabled in the current Security state.
  - Accessed at EL1 or EL0.
  - The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}.
- All of the following are true:
  - Accessed at EL0.
  - PMUSERENR_EL0.IR == 1.
Otherwise access to this field is W1S.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Otherwise:

C, bit [31]

Unsigned overflow flag for PMCCNTR_EL0 set. On writes, allows software to set the unsigned overflow flag for PMCCNTR_EL0 to 1. On reads, returns the unsigned overflow flag for PMCCNTR_EL0 overflow status.

C	Meaning
0b0	PMCCNTR_EL0 has not overflowed.
0b1	PMCCNTR_EL0 has overflowed.

PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMCCNTR_EL0[31:0] or unsigned overflow of PMCCNTR_EL0[63:0].

Accessing this field has the following behavior:

Permitted reads and writes of this field are RAZ/WI if all of the following are true:
- FEAT_PMUv3p9 is implemented.
- Accessed at EL0.
- PMUSERENR_EL0.UEN == 1.
- PMUACR_EL1.C == 0.
Permitted writes of this field are ignored if all of the following are true:
- FEAT_PMUv3p9 is implemented.
- Accessed at EL0.
- PMUSERENR_EL0.{UEN,CR} == {1,1}.
Otherwise access to this field is W1S.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

P<m>, bit [m], for m = 30 to 0

Unsigned overflow flag for PMEVCNTR<m>_EL0 set. On writes, allows software to set the unsigned overflow flag for PMEVCNTR<m>_EL0 to 1. On reads, returns the unsigned overflow flag for PMEVCNTR<m>_EL0 overflow status.

P<m>	Meaning
0b0	PMEVCNTR<m>_EL0 has not overflowed.
0b1	PMEVCNTR<m>_EL0 has overflowed.

If FEAT_PMUv3p5 is implemented, MDCR_EL2.HLP and PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMEVCNTR<m>_EL0[31:0] or unsigned overflow of PMEVCNTR<m>_EL0[63:0].

Accessing this field has the following behavior:

Permitted reads and writes of this field are RAZ/WI if any of the following are true:
- All of the following are true:
  - FEAT_PMUv3p9 is implemented.
  - Accessed at EL0.
  - PMUSERENR_EL0.UEN == 1.
  - PMUACR_EL1.P<m> == 0.
- All of the following are true:
  - EL2 is implemented and enabled in the current Security state.
  - m >= UInt(MDCR_EL2.HPMN).
  - Accessed at EL0 or EL1.
- m >= UInt(PMCR_EL0.N).
Permitted writes of this field are ignored if all of the following are true:
- FEAT_PMUv3p9 is implemented.
- Accessed at EL0.
- PMUSERENR_EL0.{UEN,ER} == {1,1}.
Otherwise access to this field is W1S.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing PMOVSSET_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMOVSSET_EL0

op0	op1	CRn	CRm	op2
0b11	0b011	0b1001	0b1110	0b011

if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0.UEN == '0') then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMOVS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMOVSSET_EL0; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMOVS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMOVSSET_EL0; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMOVSSET_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = PMOVSSET_EL0;

MSR PMOVSSET_EL0, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b011	0b1001	0b1110	0b011

if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0.UEN == '0') then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMOVS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMOVSSET_EL0 = X[t, 64]; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMOVS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMOVSSET_EL0 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMOVSSET_EL0 = X[t, 64]; elsif PSTATE.EL == EL3 then PMOVSSET_EL0 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																															F0
C	P30	P29	P28	P27	P26	P25	P24	P23	P22	P21	P20	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0

PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:33]

F<m>, bit [m+32], for m = 0
When FEAT_PMUv3_ICNTR is implemented:

Otherwise:

C, bit [31]

P<m>, bit [m], for m = 30 to 0

Accessing PMOVSSET_EL0

MRS <Xt>, PMOVSSET_EL0

MSR PMOVSSET_EL0, <Xt>

PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:33]

F<m>, bit [m+32], for m = 0When FEAT_PMUv3_ICNTR is implemented:

Otherwise:

C, bit [31]

P<m>, bit [m], for m = 30 to 0

Accessing PMOVSSET_EL0

MRS <Xt>, PMOVSSET_EL0

MSR PMOVSSET_EL0, <Xt>

F<m>, bit [m+32], for m = 0
When FEAT_PMUv3_ICNTR is implemented: