The TLBIP RVALE2IS, TLBIP RVALE2ISNXS characteristics are:
When EL2 is implemented and enabled in the current Security state, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is one of the following:
A 128-bit stage 1 translation table entry, from any level of the translation table walk up to the level indicated in the TTL hint.
A 64-bit stage 1 translation table entry, if TTL is 0b00.
The entry would be used to translate any VA in the range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)] using the EL2 or EL2&0 translation regime, as determined by the Effective value of HCR_EL2.E2H, for the Security state.
If the Effective value of HCR_EL2.E2H is not 1, the entry is from the final level of the translation table walk.
If the Effective value of HCR_EL2.E2H is 1, one of the following applies:
The entry is a global entry from the final level of the translation table walk.
The entry is a non-global entry from the final level of the translation table walk that matches the specified ASID.
The Security state is indicated by the value of SCR_EL3.NS if FEAT_RME is not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
For 128-bit translation table entry, the range of addresses invalidated is UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for the translation system is not aligned.
If FEAT_XS is implemented, the nXS variant of this System instruction is defined.
Both variants perform the same invalidation, but the TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.
The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.
This instruction is present only when FEAT_D128 is implemented. Otherwise, direct accesses to TLBIP RVALE2IS, TLBIP RVALE2ISNXS are UNDEFINED.
TLBIP RVALE2IS, TLBIP RVALE2ISNXS is a 128-bit System instruction.
| 127 | 126 | 125 | 124 | 123 | 122 | 121 | 120 | 119 | 118 | 117 | 116 | 115 | 114 | 113 | 112 | 111 | 110 | 109 | 108 | 107 | 106 | 105 | 104 | 103 | 102 | 101 | 100 | 99 | 98 | 97 | 96 |
| RES0 | BaseADDR[55:12] | ||||||||||||||||||||||||||||||
| 95 | 94 | 93 | 92 | 91 | 90 | 89 | 88 | 87 | 86 | 85 | 84 | 83 | 82 | 81 | 80 | 79 | 78 | 77 | 76 | 75 | 74 | 73 | 72 | 71 | 70 | 69 | 68 | 67 | 66 | 65 | 64 |
| BaseADDR[55:12] | |||||||||||||||||||||||||||||||
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| ASID | TG | SCALE | NUM | TTL | RES0 | ||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
Reserved, RES0.
The starting address for the range of the maintenance instructions. This field is BaseADDR[55:12] for all translation granules.
ASID value to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction.
Global TLB entries that match the VA value will be affected by this System instruction, regardless of the value of the ASID field.
If the implementation supports 16 bits of ASID, then the upper 8 bits of the ASID must be written to 0 by software when the context being invalidated only uses 8 bits.
Reserved, RES0.
Translation granule size.
| TG | Meaning |
|---|---|
| 0b00 |
Reserved. |
| 0b01 |
4K translation granule. |
| 0b10 |
16K translation granule. |
| 0b11 |
64K translation granule. |
The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.
The exponent element of the calculation that is used to produce the upper range.
The base element of the calculation that is used to produce the upper range.
TTL Level hint. The TTL hint is only guaranteed to invalidate:
Non-leaf-level entries in the range up to but not including the level described by the TTL hint.
Leaf-level entries in the range that match the level described by the TTL hint.
| TTL | Meaning |
|---|---|
| 0b00 |
The entries in the range can be using any level for the translation table entries. |
| 0b01 | The TTL hint indicates level 1. If FEAT_LPA2 is not implemented, when using a 16KB translation granule, this value is reserved and hardware should treat this field as 0b00. |
| 0b10 |
The TTL hint indicates level 2. |
| 0b11 |
The TTL hint indicates level 3. |
Reserved, RES0.
Accesses to this instruction use the following encodings in the System instruction encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b100 | 0b1000 | 0b0010 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x14); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then AArch64.TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_ISH, TLBILevel_Last, TLBI_AllAttr, X[t2, 64]:X[t, 64]); else AArch64.TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID[], Shareability_ISH, TLBILevel_Last, TLBI_AllAttr, X[t2, 64]:X[t, 64]); elsif PSTATE.EL == EL3 then if !EL2Enabled() then UNDEFINED; elsif ELIsInHost(EL2) then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2) then return; else AArch64.TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_ISH, TLBILevel_Last, TLBI_AllAttr, X[t2, 64]:X[t, 64]); else if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2) then return; else AArch64.TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID[], Shareability_ISH, TLBILevel_Last, TLBI_AllAttr, X[t2, 64]:X[t, 64]);
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b100 | 0b1001 | 0b0010 | 0b101 |
if !IsFeatureImplemented(FEAT_XS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x14); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then AArch64.TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_ISH, TLBILevel_Last, TLBI_ExcludeXS, X[t2, 64]:X[t, 64]); else AArch64.TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID[], Shareability_ISH, TLBILevel_Last, TLBI_ExcludeXS, X[t2, 64]:X[t, 64]); elsif PSTATE.EL == EL3 then if !EL2Enabled() then UNDEFINED; elsif ELIsInHost(EL2) then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2) then return; else AArch64.TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_ISH, TLBILevel_Last, TLBI_ExcludeXS, X[t2, 64]:X[t, 64]); else if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2) then return; else AArch64.TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID[], Shareability_ISH, TLBILevel_Last, TLBI_ExcludeXS, X[t2, 64]:X[t, 64]);
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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