TRCCONFIGR

AArch64 System register TRCCONFIGR bits [31:0] are architecturally mapped to External register TRCCONFIGR[31:0].

This register is present only when FEAT_ETE is implemented and System register access to the trace unit registers is implemented. Otherwise, direct accesses to TRCCONFIGR are UNDEFINED.

Attributes

Field descriptions

Bits [63:19]

ITO, bit [18]
When TRCIDR0.ITE == 1:

ITO	Meaning
0b0	Instrumentation Trace Override disabled.
0b1	Instrumentation Trace Override enabled.

Otherwise:

Bits [17:16]

VMIDOPT, bit [15]
When TRCIDR2.VMIDOPT == 0b01:

VMIDOPT	Meaning
0b0	VTTBR_EL2.VMID is used as the Virtual context identifier.
0b1	CONTEXTIDR_EL2.PROCID is used as the Virtual context identifier.

When TRCIDR2.VMIDOPT == 0b00:

When TRCIDR2.VMIDOPT == 0b10:

Otherwise:

QE, bits [14:13]
When TRCIDR0.QSUPP == 0b01:

QE	Meaning
0b00	Q elements are disabled.
0b01	Q elements with instruction counts are enabled. Q elements without instruction counts are disabled.

When TRCIDR0.QSUPP == 0b10:

QE	Meaning
0b00	Q elements are disabled.
0b11	Q elements with instruction counts are enabled. Q elements without instruction counts are enabled.

When TRCIDR0.QSUPP == 0b11:

QE	Meaning
0b00	Q elements are disabled.
0b01	Q elements with instruction counts are enabled. Q elements without instruction counts are disabled.
0b11	Q elements with instruction counts are enabled. Q elements without instruction counts are enabled.

Otherwise:

RS, bit [12]
When TRCIDR0.RETSTACK == 1:

RS	Meaning
0b0	Return stack is disabled.
0b1	Return stack is enabled.

Otherwise:

TS, bit [11]
When TRCIDR0.TSSIZE != 0b00000:

TS	Meaning
0b0	Global timestamp tracing is disabled.
0b1	Global timestamp tracing is enabled.

Otherwise:

Bits [10:8]

VMID, bit [7]
When TRCIDR2.VMIDSIZE != 0b00000:

VMID	Meaning
0b0	Virtual context identifier tracing is disabled.
0b1	Virtual context identifier tracing is enabled.

Otherwise:

CID, bit [6]
When TRCIDR2.CIDSIZE != 0b00000:

CID	Meaning
0b0	Context identifier tracing is disabled.
0b1	Context identifier tracing is enabled.

Otherwise:

Bit [5]

CCI, bit [4]
When TRCIDR0.TRCCCI == 1:

CCI	Meaning
0b0	Cycle counting instruction tracing is disabled.
0b1	Cycle counting instruction tracing is enabled.

Otherwise:

BB, bit [3]
When TRCIDR0.TRCBB == 1:

BB	Meaning
0b0	Branch broadcasting is disabled.
0b1	Branch broadcasting is enabled.

Otherwise:

Bits [2:1]

Bit [0]

Accessing TRCCONFIGR

Must always be programmed.

TRCCONFIGR.QE must be set to 0b00 if TRCCONFIGR.BB is not 0.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TRCCONFIGR

op0	op1	CRn	CRm	op2
0b10	0b001	0b0000	0b0100	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRCCONFIGR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRCCONFIGR; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRCCONFIGR;

MSR TRCCONFIGR, <Xt>

op0	op1	CRn	CRm	op2
0b10	0b001	0b0000	0b0100	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCCONFIGR = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCCONFIGR = X[t, 64]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCCONFIGR = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0													ITO	RES0		VMIDOPT	QE		RS	TS	RES0			VMID	CID	RES0	CCI	BB	RES0		RES1

TRCCONFIGR, Trace Configuration Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:19]

ITO, bit [18]
When TRCIDR0.ITE == 1:

Otherwise:

Bits [17:16]

VMIDOPT, bit [15]
When TRCIDR2.VMIDOPT == 0b01:

When TRCIDR2.VMIDOPT == 0b00:

When TRCIDR2.VMIDOPT == 0b10:

Otherwise:

QE, bits [14:13]
When TRCIDR0.QSUPP == 0b01:

When TRCIDR0.QSUPP == 0b10:

When TRCIDR0.QSUPP == 0b11:

Otherwise:

RS, bit [12]
When TRCIDR0.RETSTACK == 1:

Otherwise:

TS, bit [11]
When TRCIDR0.TSSIZE != 0b00000:

Otherwise:

Bits [10:8]

VMID, bit [7]
When TRCIDR2.VMIDSIZE != 0b00000:

Otherwise:

CID, bit [6]
When TRCIDR2.CIDSIZE != 0b00000:

Otherwise:

Bit [5]

CCI, bit [4]
When TRCIDR0.TRCCCI == 1:

Otherwise:

BB, bit [3]
When TRCIDR0.TRCBB == 1:

Otherwise:

Bits [2:1]

Bit [0]

Accessing TRCCONFIGR

MRS <Xt>, TRCCONFIGR

MSR TRCCONFIGR, <Xt>

TRCCONFIGR, Trace Configuration Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:19]

ITO, bit [18]When TRCIDR0.ITE == 1:

Otherwise:

Bits [17:16]

VMIDOPT, bit [15]When TRCIDR2.VMIDOPT == 0b01:

When TRCIDR2.VMIDOPT == 0b00:

When TRCIDR2.VMIDOPT == 0b10:

Otherwise:

QE, bits [14:13]When TRCIDR0.QSUPP == 0b01:

When TRCIDR0.QSUPP == 0b10:

When TRCIDR0.QSUPP == 0b11:

Otherwise:

RS, bit [12]When TRCIDR0.RETSTACK == 1:

Otherwise:

TS, bit [11]When TRCIDR0.TSSIZE != 0b00000:

Otherwise:

Bits [10:8]

VMID, bit [7]When TRCIDR2.VMIDSIZE != 0b00000:

Otherwise:

CID, bit [6]When TRCIDR2.CIDSIZE != 0b00000:

Otherwise:

Bit [5]

CCI, bit [4]When TRCIDR0.TRCCCI == 1:

Otherwise:

BB, bit [3]When TRCIDR0.TRCBB == 1:

Otherwise:

Bits [2:1]

Bit [0]

Accessing TRCCONFIGR

MRS <Xt>, TRCCONFIGR

MSR TRCCONFIGR, <Xt>

ITO, bit [18]
When TRCIDR0.ITE == 1:

VMIDOPT, bit [15]
When TRCIDR2.VMIDOPT == 0b01:

QE, bits [14:13]
When TRCIDR0.QSUPP == 0b01:

RS, bit [12]
When TRCIDR0.RETSTACK == 1:

TS, bit [11]
When TRCIDR0.TSSIZE != 0b00000:

VMID, bit [7]
When TRCIDR2.VMIDSIZE != 0b00000:

CID, bit [6]
When TRCIDR2.CIDSIZE != 0b00000:

CCI, bit [4]
When TRCIDR0.TRCCCI == 1:

BB, bit [3]
When TRCIDR0.TRCBB == 1: