TTBR1_EL1, Translation Table Base Register 1 (EL1)

The TTBR1_EL1 characteristics are:

Purpose

Holds the base address of the translation table for the initial lookup for stage 1 of the translation of an address from the higher VA range in the EL1&0 stage 1 translation regime, and other information for this translation regime.

Configuration

AArch64 System register TTBR1_EL1 bits [63:0] are architecturally mapped to AArch32 System register TTBR1[63:0].

TTBR1_EL1 is a 128-bit register that can also be accessed as a 64-bit value. If it is accessed as a 64-bit register, accesses read and write bits [63:0] and do not modify bits [127:64].

Attributes

TTBR1_EL1 is a:

Field descriptions

When FEAT_D128 is implemented and TCR2_EL1.D128 == 1:

12712612512412312212112011911811711611511411311211111010910810710610510410310210110099989796
RES0
9594939291908988878685848382818079787776757473727170696867666564
RES0BADDR[50:43]RES0
6362616059585756555453525150494847464544434241403938373635343332
ASIDBADDR[42:0]
313029282726252423222120191817161514131211109876543210
BADDR[42:0]RES0SKLCnP

Bits [127:88]

Reserved, RES0.

BADDR, bits [87:80, 47:5]

Translation table base address:

Address bit x is the minimum address bit required to align the translation table to the size of the table. x is calculated based on LOG2(StartTableSize), as described in VMSAv9-128. The smallest permitted value of x is 5.

The BADDR field is split as follows:

The reset behavior of this field is:

Bits [79:64]

Reserved, RES0.

ASID, bits [63:48]

An ASID for the translation table base address. The TCR_EL1.A1 field selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID.

If the implementation has only 8 bits of ASID, then the upper 8 bits of this field are RES0.

The reset behavior of this field is:

Bits [4:3]

Reserved, RES0.

SKL, bits [2:1]

Skip Level associated with translation table walks using TTBR1_EL1.

This determines the number of levels to be skipped from the regular start level of the stage 1 EL1&0 translation table walks using TTBR1_EL1.

SKLMeaning
0b00

Skip 0 level from the regular start level.

0b01

Skip 1 level from the regular start level.

0b10

Skip 2 levels from the regular start level.

0b11

Skip 3 levels from the regular start level.

The reset behavior of this field is:

CnP, bit [0]
When FEAT_TTCNP is implemented:

Common not Private. This bit indicates whether each entry that is pointed to by TBR1_EL1 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR1_EL1.CnP is 1.

CnPMeaning
0b0

The translation table entries pointed to by TTBR1_EL1, for the current translation regime and ASID, are permitted to differ from corresponding entries for TTBR1_EL1 for other PEs in the Inner Shareable domain. This is not affected by:

  • The value of TTBR1_EL1.CnP on those other PEs.

  • The value of the current ASID.

  • If EL2 is implemented and enabled in the current Security state, the value of the current VMID.

0b1

The translation table entries pointed to by TTBR1_EL1 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR1_EL1.CnP is 1 and all of the following apply:

  • The translation table entries are pointed to by TTBR1_EL1.

  • The translation tables relate to the same translation regime.

  • The ASID is the same as the current ASID.

  • If EL2 is implemented and enabled in the current Security state, the value of the current VMID.

This bit is permitted to be cached in a TLB.

When a TLB combines entries from stage 1 translation and stage 2 translation into a single entry, that entry can only be shared between different PEs if the value of the CnP bit is 1 for both stage 1 and stage 2.

Note

If the value of the TTBR1_EL1.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR1_EL1s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values'.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

When FEAT_D128 is not implemented or TCR2_EL1.D128 == 0:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
ASIDBADDR[47:1]
BADDR[47:1]CnP

ASID, bits [63:48]

An ASID for the translation table base address. The TCR_EL1.A1 field selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID.

If the implementation has only 8 bits of ASID, then the upper 8 bits of this field are RES0.

The reset behavior of this field is:

BADDR[47:1], bits [47:1]

Translation table base address:

Address bit x is the minimum address bit required to align the translation table to the size of the table. The AArch64 Virtual Memory System Architecture chapter describes how x is calculated based on the value of TCR_EL1.T1SZ, the translation stage, and the translation granule size.

If the value of TCR_EL1.IPS is not 0b110, then:

The BADDR field represents a 52-bit address if one of the following applies:

When TTBR1_EL1.BADDR represents a 52-bit addresses, all of the following apply:

Note

If BADDR represents a 52-bit address, and the translation table has fewer than eight entries, the table must be aligned to 64 bytes. Otherwise the translation table must be aligned to the size of the table.

For the 64KB granule, if FEAT_LPA is not implemented, and the value of TCR_EL1.IPS is 0b110, one the following IMPLEMENTATION DEFINED behaviors occur:

When the value of ID_AA64MMFR0_EL1.PARange indicates that the implementation supports a 56 bit PA size, bits A[55:52] of the stage 1 translation table base address are zero.

If any register bit[47:1] that is defined as RES0 has the value 1 when a translation table walk is done using TTBR1_EL1, then the translation table base address might be misaligned, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:

The reset behavior of this field is:

CnP, bit [0]
When FEAT_TTCNP is implemented:

Common not Private. This bit indicates whether each entry that is pointed to by TBR1_EL1 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR1_EL1.CnP is 1.

CnPMeaning
0b0

The translation table entries pointed to by TTBR1_EL1, for the current translation regime and ASID, are permitted to differ from corresponding entries for TTBR1_EL1 for other PEs in the Inner Shareable domain. This is not affected by:

  • The value of TTBR1_EL1.CnP on those other PEs.

  • The value of the current ASID.

  • If EL2 is implemented and enabled in the current Security state, the value of the current VMID.

0b1

The translation table entries pointed to by TTBR1_EL1 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR1_EL1.CnP is 1 and all of the following apply:

  • The translation table entries are pointed to by TTBR1_EL1.

  • The translation tables relate to the same translation regime.

  • The ASID is the same as the current ASID.

  • If EL2 is implemented and enabled in the current Security state, the value of the current VMID.

This bit is permitted to be cached in a TLB.

When a TLB combines entries from stage 1 translation and stage 2 translation into a single entry, that entry can only be shared between different PEs if the value of the CnP bit is 1 for both stage 1 and stage 2.

Note

If the value of the TTBR1_EL1.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR1_EL1s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values'.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Accessing TTBR1_EL1

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name TTBR1_EL1 or TTBR1_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TTBR1_EL1

op0op1CRnCRmop2
0b110b0000b00100b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TTBR1_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x210]; else X[t, 64] = TTBR1_EL1<63:0>; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X[t, 64] = TTBR1_EL2<63:0>; else X[t, 64] = TTBR1_EL1<63:0>; elsif PSTATE.EL == EL3 then X[t, 64] = TTBR1_EL1<63:0>;

MSR TTBR1_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b00100b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TTBR1_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x210] = X[t, 64]; else TTBR1_EL1<63:0> = X[t, 64]; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then TTBR1_EL2<63:0> = X[t, 64]; else TTBR1_EL1<63:0> = X[t, 64]; elsif PSTATE.EL == EL3 then TTBR1_EL1<63:0> = X[t, 64];

MRS <Xt>, TTBR1_EL12

op0op1CRnCRmop2
0b110b1010b00100b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X[t, 64] = NVMem[0x210]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X[t, 64] = TTBR1_EL1<63:0>; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X[t, 64] = TTBR1_EL1<63:0>; else UNDEFINED;

MSR TTBR1_EL12, <Xt>

op0op1CRnCRmop2
0b110b1010b00100b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem[0x210] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then TTBR1_EL1<63:0> = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then TTBR1_EL1<63:0> = X[t, 64]; else UNDEFINED;

When FEAT_D128 is implemented

MRRS <Xt>, <Xt+1>, TTBR1_EL1

op0op1CRnCRmop2
0b110b0000b00100b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.D128En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TTBR1_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.D128En == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif EffectiveHCR_EL2_NVx() IN {'111'} then (X[t2, 64], X[t, 64]) = Split(NVMem[0x210, 128], 64); else (X[t2, 64], X[t, 64]) = Split(TTBR1_EL1, 64); elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif ELIsInHost(EL2) then (X[t2, 64], X[t, 64]) = Split(TTBR1_EL2, 64); else (X[t2, 64], X[t, 64]) = Split(TTBR1_EL1, 64); elsif PSTATE.EL == EL3 then (X[t2, 64], X[t, 64]) = Split(TTBR1_EL1, 64);

When FEAT_D128 is implemented

MSRR TTBR1_EL1, <Xt>, <Xt+1>

op0op1CRnCRmop2
0b110b0000b00100b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.D128En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TTBR1_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.D128En == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x210, 128] = X[t2, 64]:X[t, 64]; else TTBR1_EL1<127:0> = X[t2, 64]:X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif ELIsInHost(EL2) then TTBR1_EL2<127:0> = X[t2, 64]:X[t, 64]; else TTBR1_EL1<127:0> = X[t2, 64]:X[t, 64]; elsif PSTATE.EL == EL3 then TTBR1_EL1<127:0> = X[t2, 64]:X[t, 64];

When FEAT_D128 is implemented

MRRS <Xt>, <Xt+1>, TTBR1_EL12

op0op1CRnCRmop2
0b110b1010b00100b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then (X[t2, 64], X[t, 64]) = Split(NVMem[0x210, 128], 64); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x14); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else (X[t2, 64], X[t, 64]) = Split(TTBR1_EL1, 64); else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then (X[t2, 64], X[t, 64]) = Split(TTBR1_EL1, 64); else UNDEFINED;

When FEAT_D128 is implemented

MSRR TTBR1_EL12, <Xt>, <Xt+1>

op0op1CRnCRmop2
0b110b1010b00100b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem[0x210, 128] = X[t2, 64]:X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x14); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else TTBR1_EL1<127:0> = X[t2, 64]:X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then TTBR1_EL1<127:0> = X[t2, 64]:X[t, 64]; else UNDEFINED;


26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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