EDHSR

This register is present only when FEAT_EDHSR is implemented. Otherwise, direct accesses to EDHSR are RES0.

The value of this register is UNKNOWN if the PE is in Non-debug state, or if EDSCR.STATUS is not 0b101011.

Attributes

Field descriptions

Bits [63:41]

GCS, bit [40]
When FEAT_GCS is implemented and FEAT_Debugv8p9 is implemented:

Guarded control stack data access.

Indicates that the Watchpoint debug event is due to a Guarded control stack data access.

GCS	Meaning
0b0	The Watchpoint debug event is not due to a Guarded control stack data access.
0b1	The Watchpoint debug event is due to a Guarded control stack data access.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [39:24]

WPT, bits [23:18]

Watchpoint number. When EDHSR.WPTV is 1, holds the index of a watchpoint that triggered the Watchpoint debug event.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

WPTV, bit [17]

Watchpoint number valid.

WPTV	Meaning	Applies when
0b0	EDHSR.WPT field is not valid, and holds an UNKNOWN value.	When FEAT_Debugv8p9 is not implemented
0b1	EDHSR.WPT field is valid, and holds the number of a watchpoint that triggered the Watchpoint debug event.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

WPF, bit [16]

Watchpoint might be false-positive.

WPF	Meaning	Applies when
0b0	The watchpoint matched an address or address range that was accessed by the instruction.
0b1	The watchpoint matched an address or address range that might not have been accessed by the instruction.	When FEAT_SVE is implemented or FEAT_SME is implemented

Arm strongly recommends that this bit is set to 0, other than when one of the following instructions might generate a watchpoint match for an address or address range that the instruction does not access:

An SVE contiguous vector load/store instruction, when the PE is in Streaming SVE mode.
An SME load/store instruction.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

FnP, bit [15]

EDWAR not Precise.

FnP	Meaning	Applies when
0b0	If the EDWAR is valid, it holds the virtual address of an access or sequence of contiguous accesses that triggered the Watchpoint debug event.
0b1	If the EDWAR is valid, it holds any virtual address within the smallest implemented translation granule that contains the virtual address of an access or set of contiguous accesses that triggered the Watchpoint debug event.	When FEAT_SME is implemented or FEAT_SVE is implemented

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bit [14]

VNCR, bit [13]
When FEAT_Debugv8p9 is implemented:

VNCR_EL2 access. Indicates that the Watchpoint debug event came from use of VNCR_EL2 register by EL1 code.

VNCR	Meaning	Applies when
0b0	The Watchpoint debug event was not generated by the use of VNCR_EL2 by EL1 code.
0b1	The Watchpoint debug event was generated by the use of VNCR_EL2 by EL1 code.	When FEAT_NV2 is implemented

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [12:11]

FnV, bit [10]

EDWAR not Valid.

FnV	Meaning	Applies when
0b0	EDWAR is valid.
0b1	EDWAR is not valid, and holds an UNKNOWN value.	When FEAT_SME is implemented or FEAT_SVE is implemented

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bit [9]

CM, bit [8]
When FEAT_Debugv8p9 is implemented:

Cache maintenance. Indicates whether the Watchpoint debug event came from a cache maintenance instruction.

CM	Meaning
0b0	The Watchpoint debug event was not generated by the execution of one of the System instructions identified in the description of value 1.
0b1	The Watchpoint debug event was generated by the execution of a cache maintenance instruction. The DC ZVA, DC GVA, and DC GZVA instructions are not cache maintenance instructions, and therefore do not cause this field to be set to 1.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bit [7]

WnR, bit [6]
When FEAT_Debugv8p9 is implemented:

Write not Read. Indicates whether the Watchpoint debug event was caused by an instruction writing to a memory location, or by an instruction reading from a memory location.

WnR	Meaning
0b0	Watchpoint debug event caused by an instruction reading from a memory location.
0b1	Watchpoint debug event caused by an instruction writing to a memory location.

For Watchpoint debug events on cache maintenance instructions, this field is set to 1.

For Watchpoint debug events from an atomic instruction, this field is set to 0 if a read of the location would have generated the Watchpoint debug event, otherwise it is set to 1.

If multiple watchpoints match on the same access, it is UNPREDICTABLE which watchpoint generates the Watchpoint debug event.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [5:0]

Accessing EDHSR

EDHSR can be accessed through the external debug interface:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																							GCS	RES0
RES0								WPT						WPTV	WPF	FnP	RES0	VNCR	RES0		FnV	RES0	CM	RES0	WnR	RES0

EDHSR, External Debug Halting Syndrome Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:41]

GCS, bit [40]
When FEAT_GCS is implemented and FEAT_Debugv8p9 is implemented:

Otherwise:

Bits [39:24]

WPT, bits [23:18]

WPTV, bit [17]

WPF, bit [16]

FnP, bit [15]

Bit [14]

VNCR, bit [13]
When FEAT_Debugv8p9 is implemented:

Otherwise:

Bits [12:11]

FnV, bit [10]

Bit [9]

CM, bit [8]
When FEAT_Debugv8p9 is implemented:

Otherwise:

Bit [7]

WnR, bit [6]
When FEAT_Debugv8p9 is implemented:

Otherwise:

Bits [5:0]

Accessing EDHSR

EDHSR can be accessed through the external debug interface:

EDHSR, External Debug Halting Syndrome Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:41]

GCS, bit [40]When FEAT_GCS is implemented and FEAT_Debugv8p9 is implemented:

Otherwise:

Bits [39:24]

WPT, bits [23:18]

WPTV, bit [17]

WPF, bit [16]

FnP, bit [15]

Bit [14]

VNCR, bit [13]When FEAT_Debugv8p9 is implemented:

Otherwise:

Bits [12:11]

FnV, bit [10]

Bit [9]

CM, bit [8]When FEAT_Debugv8p9 is implemented:

Otherwise:

Bit [7]

WnR, bit [6]When FEAT_Debugv8p9 is implemented:

Otherwise:

Bits [5:0]

Accessing EDHSR

EDHSR can be accessed through the external debug interface:

GCS, bit [40]
When FEAT_GCS is implemented and FEAT_Debugv8p9 is implemented:

VNCR, bit [13]
When FEAT_Debugv8p9 is implemented:

CM, bit [8]
When FEAT_Debugv8p9 is implemented:

WnR, bit [6]
When FEAT_Debugv8p9 is implemented: