GICD_IGRPMODR<n>, Interrupt Group Modifier Registers, n = 0 - 31

The GICD_IGRPMODR<n> characteristics are:

Purpose

When GICD_CTLR.DS==0, this register together with the GICD_IGROUPR<n> registers, controls whether the corresponding interrupt is in:

Secure Group 0.
Non-secure Group 1.
Secure Group 1.

Configuration

When GICD_CTLR.DS==0, these registers are Secure.

The number of implemented GICD_IGROUPR<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.

When GICD_CTLR.ARE_S==0 or GICD_CTLR.DS==1, the GICD_IGRPMODR<n> registers are RES0. An implementation can make these registers RAZ/WI in this case.

Attributes

GICD_IGRPMODR<n> is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Group_modifier_bit31	Group_modifier_bit30	Group_modifier_bit29	Group_modifier_bit28	Group_modifier_bit27	Group_modifier_bit26	Group_modifier_bit25	Group_modifier_bit24	Group_modifier_bit23	Group_modifier_bit22	Group_modifier_bit21	Group_modifier_bit20	Group_modifier_bit19	Group_modifier_bit18	Group_modifier_bit17	Group_modifier_bit16	Group_modifier_bit15	Group_modifier_bit14	Group_modifier_bit13	Group_modifier_bit12	Group_modifier_bit11	Group_modifier_bit10	Group_modifier_bit9	Group_modifier_bit8	Group_modifier_bit7	Group_modifier_bit6	Group_modifier_bit5	Group_modifier_bit4	Group_modifier_bit3	Group_modifier_bit2	Group_modifier_bit1	Group_modifier_bit0

Group_modifier_bit<x>, bit [x], for x = 31 to 0

Group modifier bit. When affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICD_IGROUPR<n> to form a 2-bit field that defines an interrupt group:

Group modifier bit	Group status bit	Definition	Short name
0b0	0b0	Secure Group 0	G0S
0b0	0b1	Non-secure Group 1	G1NS
0b1	0b0	Secure Group 1	G1S
0b1	0b1	Reserved, treated as Non-secure Group 1	-

The reset behavior of this field is:

On a GIC reset, this field resets to 0.

Additional information

For INTID m, when DIV and MOD are the integer division and modulo operations:

The corresponding GICD_IGRPMODR<n> number, n, is given by n = m DIV 32.
The offset of the required GICD_IGRPMODR is (0x080 + (4*n)).
The bit number of the required group modifier bit in this register is m MOD 32.

See GICD_IGROUPR<n> for information about the GICD_IGRPMODR0 reset value.

Accessing GICD_IGRPMODR<n>

When affinity routing is enabled for Secure state, GICD_IGRPMODR0 is RES0 and equivalent functionality is proved by GICR_IGRPMODR0.

When GICD_CTLR.DS==0, the register is RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

Note

Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.

GICD_IGRPMODR<n> can be accessed through the memory-mapped interfaces:

Component	Frame	Offset	Instance
GIC Distributor	Dist_base	0x0D00 + (4 * n)	GICD_IGRPMODR<n>

Accesses on this interface are RW.

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6