The GICR_IGRPMODR0 characteristics are:
When GICD_CTLR.DS==0, this register together with the GICR_IGROUPR0 register, controls whether the corresponding interrupt is in:
When GICD_CTLR.DS==0, this register is Secure.
A copy of this register is provided for each Redistributor.
GICR_IGRPMODR0 is a 32-bit register.
Group modifier bit. In implementations where affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICR_IGROUPR0 to form a 2-bit field that defines an interrupt group:
| Group modifier bit | Group status bit | Definition | Short name |
|---|---|---|---|
| 0b0 | 0b0 | Secure Group 0 | G0S |
| 0b0 | 0b1 | Non-secure Group 1 | G1NS |
| 0b1 | 0b0 | Secure Group 1 | G1S |
| 0b1 | 0b1 | Reserved, treated as Non-secure Group 1 | - |
The reset behavior of this field is:
When affinity routing is not enabled for the Security state of an interrupt in GICR_IGRPMODR0, the corresponding bit is RES0 and equivalent functionality is provided by GICD_IGRPMODR<n> with n=0.
This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_IGRPMODR<n>.
When GICD_CTLR.ARE_S == 0 or GICD_CTLR.DS == 1, GICR_IGRPMODR0 is RES0. An implementation can make this register RAZ/WI in this case.
When GICD_CTLR.DS==0, the register is RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | SGI_base | 0x0D00 | GICR_IGRPMODR0 |
Accesses on this interface are RW.
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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