GICD_ISENABLER<n>E, Interrupt Set-Enable Registers, n = 0 - 31

The GICD_ISENABLER<n>E characteristics are:

Purpose

Enables forwarding of the corresponding SPI in the extended SPI range to the CPU interfaces.

This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICD_ISENABLER<n>E are RES0.

When GICD_TYPER.ESPI==0, these registers are RES0.

When GICD_TYPER.ESPI==1, the number of implemented GICD_ISENABLER<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.

GICD_ISENABLER<n>E is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Set_enable_bit31	Set_enable_bit30	Set_enable_bit29	Set_enable_bit28	Set_enable_bit27	Set_enable_bit26	Set_enable_bit25	Set_enable_bit24	Set_enable_bit23	Set_enable_bit22	Set_enable_bit21	Set_enable_bit20	Set_enable_bit19	Set_enable_bit18	Set_enable_bit17	Set_enable_bit16	Set_enable_bit15	Set_enable_bit14	Set_enable_bit13	Set_enable_bit12	Set_enable_bit11	Set_enable_bit10	Set_enable_bit9	Set_enable_bit8	Set_enable_bit7	Set_enable_bit6	Set_enable_bit5	Set_enable_bit4	Set_enable_bit3	Set_enable_bit2	Set_enable_bit1	Set_enable_bit0

For the extended SPI range, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior:

Set_enable_bit<x>	Meaning
0b0	If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect.
0b1	If read, indicates that forwarding of the corresponding interrupt is enabled. If written, enables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 1.

Set_enable_bit<x>

Meaning

0b0

If read, indicates that forwarding of the corresponding interrupt is disabled.

If written, has no effect.

0b1

If read, indicates that forwarding of the corresponding interrupt is enabled.

If written, enables forwarding of the corresponding interrupt.

After a write of 1 to this bit, a subsequent read of this bit returns 1.

The reset behavior of this field is:

For INTID m, when DIV and MOD are the integer division and modulo operations:

The corresponding GICD_ISENABLER<n>E number, n, is given by n = (m-4096) DIV 32.
The offset of the required GICD_ISENABLER<n>E is (0x1200 + (4*n)).
The bit number of the required group modifier bit in this register is (m-4096) MOD 32.

When affinity routing is not enabled for the Security state of an interrupt in GICD_ISENABLER<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

Component	Frame	Offset	Instance
GIC Distributor	Dist_base	0x1200 + (4 * n)	GICD_ISENABLER<n>E

Accesses on this interface are RW.

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6