The GICR_INVLPIR characteristics are:
Invalidates the cached configuration data of a specified LPI, causing the GIC to reload the interrupt configuration from the appropriate LPI Configuration table.
A copy of this register is provided for each Redistributor.
GICR_INVLPIR is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
V | RES0 | vPEID | |||||||||||||||||||||||||||||
INTID |
Indicates whether the INTID is virtual or physical.
V | Meaning |
---|---|
0b0 |
Invalidate is for a physical INTID. |
0b1 |
Invalidate is for a virtual INTID. |
Reserved, RES0.
Reserved, RES0.
When GICR_INVLPIR.V == 0, this field is RES0
When GICR_INVLPIR.V == 1, this field is the target vPEID of the invalidate.
The size of this field is IMPLEMENTATION DEFINED, and is specified by the GICD_TYPER2.VIL and GICD_TYPER2.VID fields. Unimplemented bits are RES0.
Reserved, RES0.
The INTID of the LPI to be invalidated.
The size of this field is IMPLEMENTATION DEFINED, and is specified by the GICD_TYPER.IDbits field. Unimplemented bits are RES0.
If any LPI has been forwarded to the PE and a valid write to GICR_INVLPIR is received, the Redistributor must ensure it reloads its properties from memory and apply any changes by retrieving and reforwarding the LPI as required. This has no effect on the forwarded LPI if it has already been activated.
When written with a 32-bit write the data is zero-extended to 64 bits.
This register is mandatory when any of the following are true:
Otherwise, the functionality is IMPLEMENTATION DEFINED.
Writes to this register have no effect if either:
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | RD_base | 0x00A0 | GICR_INVLPIR |
Accesses on this interface are WO.
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.