GICR_TYPER

The identity of the PE associated with this Redistributor.

Bits [63:56] provide Aff3, the Affinity level 3 value for the Redistributor.

Bits [55:48] provide Aff2, the Affinity level 2 value for the Redistributor.

Bits [47:40] provide Aff1, the Affinity level 1 value for the Redistributor.

Bits [39:32] provide Aff0, the Affinity level 0 value for the Redistributor.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

PPInum, bits [31:27]
When GICv3.1 is implemented:

The value derived from this field specifies the maximum PPI INTID that a GIC implementation can support. An implementation might not implement all PPIs up to this maximum.

The value of this field is an IMPLEMENTATION DEFINED choice of:

PPInum	Meaning
0b00000	Maximum PPI INTID is 31.
0b00001	Maximum PPI INTID is 1087.
0b00010	Maximum PPI INTID is 1119.

All other values are reserved.

Access to this field is RO.

Otherwise:

VSGI, bit [26]
When GICv4.1 is implemented:

Indicates whether vSGIs are supported.

The value of this field is an IMPLEMENTATION DEFINED choice of:

VSGI	Meaning
0b0	Direct injection of SGIs not supported.
0b1	Direct injection of SGIs supported.

Access to this field is RO.

Otherwise:

CommonLPIAff, bits [25:24]

Indicates the scope of the CommonLPIAff group.

The value of this field is an IMPLEMENTATION DEFINED choice of:

CommonLPIAff	Meaning
0b00	All Redistributors are members of the same CommonLPIAff group.
0b01	All Redistributors with the same Aff3 value are members of the same CommonLPIAff group.
0b10	All Redistributors with the same Aff3.Aff2 value are members of the same CommonLPIAff group.
0b11	All Redistributors with the same Aff3.Aff2.Aff1 value are members of the same CommonLPIAff group.

Redistributors in the same CommonLPIAff group must use the same copy of the LPI Configuration table, and if GICv4.1 is implemented the same copy of the vPE Configuration table.

Access to this field is RO.

Processor_Number, bits [23:8]

A unique identifier for the PE. When GITS_TYPER.PTA == 0, an ITS uses this field to identify the interrupt target.

When affinity routing is disabled for a Security state, this field indicates which GICD_ITARGETSR<n> corresponds to this Redistributor.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

RVPEID, bit [7]
When GICv4.1 is implemented:

Indicates how the resident vPE is specified.

The value of this field is an IMPLEMENTATION DEFINED choice of:

RVPEID	Meaning
0b0	GICR_VPENDBASER records the address of the vPE's Virtual Pending Table.
0b1	GICR_VPENDBASER records vPEID.

Access to this field is RO.

Otherwise:

MPAM, bit [6]
When GICv3.1 is implemented:

MPAM

The value of this field is an IMPLEMENTATION DEFINED choice of:

MPAM	Meaning
0b0	MPAM not supported.
0b1	MPAM supported.

Access to this field is RO.

Otherwise:

DPGS, bit [5]

Sets support for GICR_CTLR.DPG* bits.

The value of this field is an IMPLEMENTATION DEFINED choice of:

DPGS	Meaning
0b0	GICR_CTLR.DPG* bits are not supported.
0b1	GICR_CTLR.DPG* bits are supported.

Access to this field is RO.

Last, bit [4]

Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages.

The value of this field is an IMPLEMENTATION DEFINED choice of:

Last	Meaning
0b0	This Redistributor is not the highest-numbered Redistributor in a series of contiguous Redistributor pages.
0b1	This Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages.

Access to this field is RO.

DirectLPI, bit [3]

Indicates whether this Redistributor supports direct injection of LPIs.

The value of this field is an IMPLEMENTATION DEFINED choice of:

DirectLPI	Meaning
0b0	This Redistributor does not support direct injection of LPIs. The GICR_SETLPIR, GICR_CLRLPIR, GICR_INVLPIR, GICR_INVALLR, and GICR_SYNCR registers are either not implemented, or have an IMPLEMENTATION DEFINED purpose.
0b1	This Redistributor supports direct injection of LPIs. The GICR_SETLPIR, GICR_CLRLPIR, GICR_INVLPIR, GICR_INVALLR, and GICR_SYNCR registers are implemented.

Access to this field is RO.

Dirty, bit [2]

Controls the functionality of GICR_VPENDBASER.Dirty.

The value of this field is an IMPLEMENTATION DEFINED choice of:

Dirty	Meaning
0b0	GICR_VPENDBASER.Dirty is UNKNOWN when GICR_VPENDBASER.Valid == 1.
0b1	GICR_VPENDBASER.Dirty indicates when the Virtual Pending Table has been parsed when GICR_VPENDBASER.Valid is written from 0 to 1.

When GICR_TYPER.VLPIS == 0, this field is RES0.

Note

In GICv4p1 implementations this field is RES1.

Access to this field is RO.

VLPIS, bit [1]

Indicates whether the GIC implementation supports virtual LPIs and the direct injection of virtual LPIs.

The value of this field is an IMPLEMENTATION DEFINED choice of:

VLPIS	Meaning
0b0	The implementation does not support virtual LPIs or the direct injection of virtual LPIs.
0b1	The implementation supports virtual LPIs and the direct injection of virtual LPIs.

Note

In GICv3 implementations this field is RES0.

Access to this field is RO.

PLPIS, bit [0]

Indicates whether the GIC implementation supports physical LPIs.

The value of this field is an IMPLEMENTATION DEFINED choice of:

PLPIS	Meaning
0b0	The implementation does not support physical LPIs.
0b1	The implementation supports physical LPIs.

Access to this field is RO.

Accessing GICR_TYPER

GICR_TYPER can be accessed through the memory-mapped interfaces:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Affinity_Value
PPInum					VSGI	CommonLPIAff		Processor_Number																RVPEID	MPAM	DPGS	Last	DirectLPI	Dirty	VLPIS	PLPIS

GICR_TYPER, Redistributor Type Register

Purpose

Configuration

Attributes

Field descriptions

Affinity_Value, bits [63:32]

PPInum, bits [31:27]
When GICv3.1 is implemented:

Otherwise:

VSGI, bit [26]
When GICv4.1 is implemented:

Otherwise:

CommonLPIAff, bits [25:24]

Processor_Number, bits [23:8]

RVPEID, bit [7]
When GICv4.1 is implemented:

Otherwise:

MPAM, bit [6]
When GICv3.1 is implemented:

Otherwise:

DPGS, bit [5]

Last, bit [4]

DirectLPI, bit [3]

Dirty, bit [2]

VLPIS, bit [1]

PLPIS, bit [0]

Accessing GICR_TYPER

GICR_TYPER can be accessed through the memory-mapped interfaces:

GICR_TYPER, Redistributor Type Register

Purpose

Configuration

Attributes

Field descriptions

Affinity_Value, bits [63:32]

PPInum, bits [31:27]When GICv3.1 is implemented:

Otherwise:

VSGI, bit [26]When GICv4.1 is implemented:

Otherwise:

CommonLPIAff, bits [25:24]

Processor_Number, bits [23:8]

RVPEID, bit [7]When GICv4.1 is implemented:

Otherwise:

MPAM, bit [6]When GICv3.1 is implemented:

Otherwise:

DPGS, bit [5]

Last, bit [4]

DirectLPI, bit [3]

Dirty, bit [2]

VLPIS, bit [1]

PLPIS, bit [0]

Accessing GICR_TYPER

GICR_TYPER can be accessed through the memory-mapped interfaces:

PPInum, bits [31:27]
When GICv3.1 is implemented:

VSGI, bit [26]
When GICv4.1 is implemented:

RVPEID, bit [7]
When GICv4.1 is implemented:

MPAM, bit [6]
When GICv3.1 is implemented: