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GICR_ISPENDR0, Interrupt Set-Pending Register 0

The GICR_ISPENDR0 characteristics are:

Purpose

Adds the pending state to the corresponding SGI or PPI.

Configuration

A copy of this register is provided for each Redistributor.

Attributes

GICR_ISPENDR0 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
Set_pending_bit31Set_pending_bit30Set_pending_bit29Set_pending_bit28Set_pending_bit27Set_pending_bit26Set_pending_bit25Set_pending_bit24Set_pending_bit23Set_pending_bit22Set_pending_bit21Set_pending_bit20Set_pending_bit19Set_pending_bit18Set_pending_bit17Set_pending_bit16Set_pending_bit15Set_pending_bit14Set_pending_bit13Set_pending_bit12Set_pending_bit11Set_pending_bit10Set_pending_bit9Set_pending_bit8Set_pending_bit7Set_pending_bit6Set_pending_bit5Set_pending_bit4Set_pending_bit3Set_pending_bit2Set_pending_bit1Set_pending_bit0

Set_pending_bit<x>, bit [x], for x = 31 to 0

For PPIs and SGIs, adds the pending state to interrupt number x. Reads and writes have the following behavior:

Set_pending_bit<x>Meaning
0b0

If read, indicates that the corresponding interrupt is not pending on this PE.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is pending, or active and pending on this PE.

If written, changes the state of the corresponding interrupt from inactive to pending, or from active to active and pending. This has no effect in the following cases:

  • If the interrupt is already pending because of a write to GICR_ISPENDR0.
  • If the interrupt is already pending because the corresponding interrupt signal is asserted. In this case, the interrupt remains pending if the interrupt signal is deasserted.

The reset behavior of this field is:

Accessing GICR_ISPENDR0

When affinity routing is not enabled for the Security state of an interrupt in GICR_ISPENDR0, the corresponding bit is RAZ/WI and equivalent functionality is provided by GICD_ISPENDR<n> with n=0.

This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_ISPENDR<n>.

When GICD_CTLR.DS == 0, bits corresponding to Secure SGIs and PPIs are RAZ/WI to Non-secure accesses.

GICR_ISPENDR0 can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorSGI_base0x0200GICR_ISPENDR0

Accesses on this interface are RW.

AArch32 Registers
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AArch32 Instructions
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26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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