The TRCBBCTLR characteristics are:
Controls the regions in the memory map where branch broadcasting is active.
External register TRCBBCTLR bits [31:0] are architecturally mapped to AArch64 System register TRCBBCTLR[31:0].
This register is present only when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented, TRCIDR0.TRCBB == 1 and UInt(TRCIDR4.NUMACPAIRS) > 0. Otherwise, direct accesses to TRCBBCTLR are RES0.
TRCBBCTLR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | MODE | RANGE[7] | RANGE[6] | RANGE[5] | RANGE[4] | RANGE[3] | RANGE[2] | RANGE[1] | RANGE[0] |
Reserved, RES0.
Mode.
MODE | Meaning |
---|---|
0b0 | Exclude Mode. Branch broadcasting is not active for instructions in the address ranges defined by TRCBBCTLR.RANGE. If TRCBBCTLR.RANGE == 0x00 then branch broadcasting is active for all instructions. |
0b1 | Include Mode. Branch broadcasting is active for instructions in the address ranges defined by TRCBBCTLR.RANGE. If TRCBBCTLR.RANGE == 0x00 then the behavior of the trace unit is CONSTRAINED UNPREDICTABLE. That is, the trace unit might or might not consider any instructions to be in a branch broadcasting region. |
The reset behavior of this field is:
Selects whether Address Range Comparator <m> is used with branch broadcasting.
RANGE[<m>] | Meaning |
---|---|
0b0 |
The address range that Address Range Comparator <m> defines, is not selected. |
0b1 |
The address range that Address Range Comparator <m> defines, is selected. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Must be programmed if TRCCONFIGR.BB == 1.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Component | Offset | Instance |
---|---|---|
ETE | 0x03C | TRCBBCTLR |
This interface is accessible as follows:
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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